ADFS7124-8BBCPZ datasheet(87/93 Pages) AD

87 / 93 page

Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Rev. 0 | 87 of 93

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (0)

MCLK_CNT_

EN (0)

LDO_CAP_CHK_TE

ST_EN (0)

LDO_CAP_CHK (0)

ADC_CAL_ERR_ EN

(0)

ADC_CONV_ERR_

EN (0)

ADC_SAT_ ERR_EN

(0)

AINP_OV_

ERR_EN (0)

AINP_UV_

ERR_EN (0)

AINM_OV_ERR_ EN

(0)

AINM_UV_

ERR_EN (0)

REF_DET_ERR_

EN (0)

DLDO_PSM_

TRIP_TEST_EN (0)

DLDO_PSM_ERR_

EN (0)

ALDO_PSM_

TRIP_TEST_EN (0)

ALDO_PSM_

ERR_EN (0)

SPI_IGNORE_

ERR_EN (1)

SPI_SCLK_CNT_

ERR_EN (0)

SPI_READ_

ERR_EN (0)

SPI_WRITE_

ERR_EN (0)

SPI_CRC_ERR_ EN

(0)

MM_CRC_ERR_ EN

(0)

ROM_CRC_ERR_ EN

(0)

Table 71. ERROR_EN Register Bit Descriptions

Bits

Bit Name

Description

This bit must be programmed with a Logic 0 for correct operation.

MCLK_CNT_EN

Controller clock counter. When this bit is set, the controller clock counter is enabled and the result is reported through the

MCLK_COUNT register. The counter monitors the controller clock being used by the ADC. If an external clock is the clock

source, the MCLK counter monitors this external clock. Similarly, if the on-chip oscillator is selected as the clock source to

the ADC, the MCLK counter monitors the on-chip oscillator.

LDO_CAP_CHK_TEST_EN

Test of analog/digital LDO decoupling capacitor check. When this bit is set, the decoupling capacitor is internally

disconnected from the LDO, forcing a fault condition. This allows the user to test the circuitry that is used for the analog

and digital LDO decoupling capacitor check.

20:19

LDO_CAP_CHK

Analog/digital LDO decoupling capacitor check. These bits enable the capacitor check. When a check is enabled, the ADC

checks for the presence of the external decoupling capacitor on the selected supply. When the check is complete, the

LDO_CAP_CHK bits are both reset to 0. Note that a missing decoupling capacitor can cause the ADC to reset. However, a

missing capacitor is easily detectable at the system level.

00 = check is not enabled.

01 = check the analog LDO capacitor.

10 = check the digital LDO capacitor.

11 = check is not enabled.

ADC_CAL_ERR_EN

When this bit is set, the calibration fail check is enabled.

ADC_CONV_ERR_EN

When this bit is set, the conversions are monitored and the ADC_CONV_ERR bit is set when a conversion fails.

ADC_SAT_ERR_EN

When this bit is set, the ADC modulator saturation check is enabled.

AINP_OV_ERR_EN

When this bit is set, the overvoltage monitor on all enabled AINP channels is enabled.

AINP_UV_ERR_EN

When this bit is set, the undervoltage monitor on all enabled AINP channels is enabled.

AINM_OV_ERR_EN

When this bit is set, the overvoltage monitor on all enabled AINM channels is enabled.

AINM_UV_ERR_EN

When this bit is set, the undervoltage monitor on all enabled AINM channels is enabled.

REF_DET_ERR_EN

When this bit is set, any external reference being used by the ADC is continuously monitored. An error is flagged if the

external reference is open circuit or has a value of less than 0.7 V.

DLDO_PSM_TRIP_TEST_EN

Checks the test mechanism that monitors the digital LDO. When this bit is set, the input to the test circuit is tied to DGND

instead of the LDO output. Set the DLDO_PSM_ERR bit in the error register.

DLDO_PSM_ERR_ERR_EN

When this bit is set, the digital LDO voltage is continuously monitored. The DLDO_PSM_ERR bit in the error register is set

if the voltage being output from the digital LDO is outside specification.

ALDO_PSM_TRIP_TEST_EN

Checks the test mechanism that monitors the analog LDO. When this bit is set, the input to the test circuit is tied to AVSS

instead of the LDO output. Set the ALDO_PSM_ERR bit in the error register.

ALDO_PSM_ERR_EN

When this bit is set, the analog LDO voltage is continuously monitored. The ALDO_PSM_ERR bit in the error register is set

if the voltage being output from the analog LDO is outside specification.

SPI_IGNORE_ERR_EN

During power-on reset and calibrations, the on-chip registers cannot be written to. User write instructions are ignored by

the ADC. Set this bit so that the SPI_IGNORE_ERR bit in the error register informs when write operations are ignored.

SPI_SCLK_CNT_ERR_EN

When this bit is set, the SCLK counter is enabled. All read and write operations to the ADC are multiples of eight bits.

For every serial communication, the SCLK counter counts the number of SCLK pulses. CS must be used to frame each

read and write operation. If the number of SCLK pulses used during a communication is not a multiple of eight, the

SPI_SCLK_CNT_ERR bit in the error register is set. For example, a glitch on the SCLK pin during a read or write operation

can be interpreted as an SCLK pulse. In this case, the SPI_SCLK_CNT_ERR bit is set as there is an excessive number of

SCLK pulses detected. CS_EN in the ADC_CONTROL register must be set to 1 when the SCLK counter function is being

used.

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