ADFS7124-8BBCPZ datasheet(38/93 Pages) AD

38 / 93 page

Data Sheet

ADFS7124-8

GETTING STARTED

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Rev. 0 | 38 of 93

DRIVE EDGE

SAMPLE EDGE

Figure 65. SPI Mode 3, SCLK Edges

Accessing the ADC Register Map

The communications register controls access to the full register

map of the ADC. This register is an 8-bit, write only register. On

power-up or after a reset, the digital interface defaults to a state

where it expects a write to the communications register; therefore,

all communication begins by writing to the communications register.

The data written to the communications register determines which

to which the read or write operation applies.

When the read or write operation to the selected register is com-

plete, the interface returns to its default state, where it expects a

write operation to the communications register.

In situations where interface synchronization is lost, a write opera-

tion of at least 64 serial clock cycles with DIN high returns the ADC

to its default state by resetting the entire device, including the regis-

ter contents. Alternatively, if CS is used with the digital interface,

returning CS high resets the digital interface to its default state and

aborts any current operation.

Figure 66 and Figure 67 illustrate writing to and reading from a

Reading the ID register is the recommended method for verifying

correct communication with the device. The ID register is a read

only register and contains the value of 0x17 for the ADFS7124-8.

The communication register and ID register details are described in

Table 37 and Table 38.

DIN

SCLK

8-BIT COMMAND

8 BITS, 16 BITS,

OR 24 BITS OF DATA

CMD

DATA

Figure 66. Writing to a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on

the Register Selected)

DIN

SCLK

8-BIT COMMAND

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OUTPUT

CMD

DATA

DOUT/RDY

Figure 67. Reading from a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, 24 Bits, or 32 Bits; Data Length on DOUT

Is Dependent on the Register Selected, CRC Enabled)

Table 37. Communications Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x00

COMMS

[7:0]

WEN

R/W

RS[5:0]

0x00

Table 38. ID Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x05

[7:0]

DEVICE_ID

SILICON_REVISION

0x17

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