ADFS7124-8BBCPZ datasheet(51/93 Pages) AD

51 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 51 of 93

the conversion each time that the data read is performed. The

four LSBs of the status register indicate the channel to which the

conversion corresponds.

Continuous Conversion Mode

Continuous conversion is the default power-up mode. The

ADFS7124-8 converts continuously, and the RDY bit in the status

the DOUT/RDY line also goes low when a conversion is complete.

To read a conversion, write to the communications register, indicat-

ing that the next operation is a read of the data register. When the

data-word is read from the data register, DOUT/RDY goes high.

Read this register additional times, if required. However, ensure

that the data register is not being accessed at the completion of the

next conversion; otherwise the new conversion word is lost.

When several channels are enabled, the ADC automatically se-

quences through the enabled channels, performing one conversion

on each channel. When all channels are converted, the sequence

starts again with the first channel. The channels are converted

in order from the lowest enabled channel to the highest enabled

channel. The data register is updated as soon as each conversion

is available. The DOUT/RDY pin pulses low each time a conversion

is available. Then read the conversion while the ADC converts the

next enabled channel.

If the DATA_STATUS bit in the ADC_CONTROL register is set to 1,

the contents of the status register, along with the conversion data,

are output each time the data register is read. The status register

indicates the channel to which the conversion corresponds.

DIN

SCLK

DOUT/RDY

0x01

0x0004

0x42

DATA

Figure 78. Single Conversion Configuration

DIN

SCLK

DOUT/RDY

0x42

DATA

Figure 79. Continuous Conversion Configuration

DIN

SCLK

DOUT/RDY

DATA

0x01

0x0800

Figure 80. Continuous Read Configuration

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