ADFS7124-8BBCPZ datasheet(61/93 Pages) AD

61 / 93 page

Data Sheet

ADFS7124-8

DIGITAL FILTER

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Rev. 0 | 61 of 93

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data rate.

CONVERSIONS

CHANNEL A

CHANNEL

CHANNEL B

CH A CH A CH A CH A

CH A

CH B CH B

1/fADC DT/fCLK

NOTES

1. DT = DEAD TIME.

Figure 98. Fast Settling, Sinc4 + Sinc1 Filter

When the device is converting on a single channel and a step

change occurs on the analog input, the ADC does not detect the

change and continues to output conversions. If the step change is

synchronized with the conversion, there is one intermediate result,

which is not completely settled (see Figure 99). If the step change

is asynchronous to the conversion process, there is one or two

intermediate results, which are not completely settled.

ANALOG

INPUT

ADC

OUTPUT

VALID

fADC

Figure 99. Step Change on the Analog Input, Sinc4 + Sinc1 Filter

Sequencer

The description in the Fast Settling Mode (Sinc4 + Sinc1 Filter)

section is valid when manually switching channels, for example,

writing to the device to change channels. When multiple channels

are enabled, the on-chip sequencer is automatically used; the

device automatically sequences between all enabled channels. In

this case, the first conversion takes the complete settling time, as

listed in Table 59. For all subsequent conversions, the time needed

for each conversion is also the settling time, but the dead time is

reduced to 30.

50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter

Figure 100 shows the frequency response when FS[10:0] is set to

24 in the full power mode, or 6 in the mid power mode or low power

mode. Table 59 lists the corresponding output data rate. The sinc

filter places the first notch at:

fNOTCH = fCLK/(32 × FS[10:0])

The sinc1 filter places notches at fNOTCH/Avg (Avg equaling 16 for

the full power mode and mid power mode, and equaling 8 for the

low power mode). Notches are also placed at multiples of this

frequency; therefore, when FS[10:0] is set to 24 in the full power

mode or 6 in the mid power mode, a notch is placed at 800 Hz

due to the sinc filter, and notches are placed at 50 Hz and multiples

of 50 Hz due to the averaging. In the low power mode, a notch is

placed at 400 Hz due to the sinc filter, and notches are placed at 50

Hz and multiples of 50 Hz due to the averaging.

The notch at 50 Hz is a first-order notch; therefore, the notch is

not wide. This means that the rejection at 50 Hz exactly is good,

assuming a stable controller clock. However, in a band of 50 Hz ± 1

Hz, the rejection degrades significantly. The rejection at 50 Hz ± 0.5

Hz is 40 dB minimum, assuming a stable clock; therefore, a good

controller clock source is recommended when using the fast settling

mode.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 100. 50 Hz Rejection

Figure 101 shows the filter response when FS[10:0] is set to 20 in

the full power mode, or 5 in the mid power and low power modes.

In this case, a notch is placed at 60 Hz and multiples of 60 Hz. The

rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 101. 60 Hz Rejection

Simultaneous 50 Hz/60 Hz rejection is achieved when FS[10:0] is

set to 120 in the full power mode, or 30 in the mid power and

low power modes. Notches are placed at 10 Hz and multiples of

10 Hz, thereby giving simultaneous 50 Hz and 60 Hz rejection. The

rejection at 50 Hz ± 0.5 Hz and 60 Hz ± 0.5 Hz is 44 dB typically.

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