ADFS7124-8BBCPZ datasheet(73/93 Pages) AD

73 / 93 page

Data Sheet

ADFS7124-8

GROUNDING AND LAYOUT

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Rev. 0 | 73 of 93

The analog inputs and reference inputs are differential and, there-

fore, most of the voltages in the analog modulator are common-

mode voltages. The high common-mode rejection of the device

removes common-mode noise on these inputs. The analog and

digital supplies to the ADFS7124-8 are independent and separately

pinned out to minimize coupling between the analog and digital

sections of the device. The digital filter provides rejection of broad-

band noise on the power supplies, except at integer multiples of the

controller clock frequency.

The digital filter also removes noise from the analog and reference

inputs, provided that these noise sources do not saturate the

analog modulator. As a result, the ADFS7124-8 is more immune

to noise interference than a conventional high resolution converter.

However, because the resolution of the ADFS7124-8 is high and

the noise levels from the converter are so low, care must be taken

with regard to grounding and layout.

The PCB that houses the ADC must be designed so that the analog

and digital sections are separated and confined to certain areas of

the board. A minimum etch technique is generally best for ground

planes because it results in the best shielding.

In any layout, keep in mind the flow of currents in the system,

ensuring that the paths for all return currents are as close as

possible to the paths the currents took to reach their destinations.

Avoid running digital lines under the device because this couples

noise onto the die and allows the analog ground plane to run under

the ADFS7124-8 to prevent noise coupling. The power supply lines

to the ADFS7124-8 must use as wide a trace as possible to provide

low impedance paths and reduce glitches on the power supply

line. Shield fast switching signals like clocks with digital ground to

prevent radiating noise to other sections of the board and never

run clock signals near the analog inputs. Avoid crossover of digital

and analog signals. Run traces on opposite sides of the board at

right angles to each other. This reduces the effects of feedthrough

on the board. A microstrip technique is by far the best but is

not always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground planes,

whereas signals are placed on the solder side.

Good decoupling is important when using high resolution ADCs.

The ADFS7124-8 has two power supply pins, AVDD and IOVDD. The

AVDD pin is referenced to AVSS, and the IOVDD pin is referenced to

DGND. Decouple AVDD with a 1 µF tantalum capacitor in parallel

with a 0.1 µF capacitor to AVSS on each pin. Place the 0.1 µF

capacitor as close as possible to the device on each supply, ideally

right up against the device. Decouple IOVDD with a 1 µF tantalum

capacitor in parallel with a 0.1 µF capacitor to DGND. All analog

inputs must be decoupled to AVSS. If an external reference is used,

decouple the REFINx(+) and REFINx(−) pins to AVSS.

The ADFS7124-8 also has two on-board LDO regulators, one that

regulates the AVDD supply and one that regulates the IOVDD supply.

For the REGCAPA pin, it is recommended that a 0.1 µF capacitor to

AVSS be used. Similarly, for the REGCAPD pin, it is recommended

that a 0.1 µF capacitor to DGND be used.

If using the ADFS7124-8 with split supply operation, a separate

plane must be used for AVSS.

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