ADFS7124-8BBCPZ datasheet(55/93 Pages) AD

55 / 93 page

Data Sheet

ADFS7124-8

DIGITAL FILTER

analog.com

Rev. 0 | 55 of 93

Table 54. Filter Registers

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x21 to

0x28

FILTER_0 to

FILTER_7

Filter

REJ60

POST_FILTER

SINGLE_CYCLE

0x060180

FS[10:8]

FS[7:0]

The ADFS7124-8 offers a great deal of flexibility in the digital filter.

The device has several filter options. The option selected affects

the output data rate, settling time, and 50 Hz and 60 Hz rejection.

The following sections describe each filter type, indicating the

available output data rates for each filter option. The filter response

along with the settling time and 50 Hz and 60 Hz rejection is also

discussed.

The filter bits in the filter register select between the sinc type filter.

SINC4 FILTER

When the ADFS7124-8 is powered up, the sinc4 filter is selected

by default. This filter gives excellent noise performance over the

complete range of output data rates. It also gives the best 50 Hz/ 60

Hz rejection, but it has a long settling time. In Figure 81, the blocks

shown in gray are unused.

SINC3 /SINC4

FILTER

MODULATOR

AVERAGING

BLOCK

POST

FILTER

Figure 81. Sinc4 Filter

Sinc4 Output Data Rate/Settling Time

The output data rate (the rate at which conversions are available on

a single channel when the ADC is continuously converting) is equal

to:

fADC = fCLK/(32 × FS[10:0])

where:

fADC is the output data rate.

fCLK is the controller clock frequency (614.4 kHz in full power mode,

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the filter

The output data rate can be programmed from:

►

9.38 SPS to 19,200 SPS for full power mode

►

2.35 SPS to 4800 SPS for mid power mode

►

1.17 SPS to 2400 SPS for low power mode

The settling time for the sinc4 filter is equal to:

tSETTLE = (4 × 32 × FS[10:0] + Dead Time)/fCLK

where, Dead Time = 61 when FS[10:0] = 1 and 95 when FS[10:0] >

When a channel change occurs, the modulator and filter are reset.

The settling time is allowed to generate the first conversion after the

channel change. Subsequent conversions on this channel occur at

1/fADC.

CONVERSIONS

CHANNEL A

CHANNEL

CHANNEL B

CH A CH A

CH A

CH B CH B

CH B

1/fADC

DT/

fCLK

NOTES

1. DT = DEAD TIME.

Figure 82. Sinc4 Channel Change

When conversions are performed on a single channel and a step

change occurs, the ADC does not detect the change in the analog

input. Therefore, it continues to output conversions at the program-

med output data rate. However, it is at least four conversions later

before the output data accurately reflects the analog input. If the

step change occurs while the ADC is processing a conversion, then

the ADC takes five conversions after the step change to generate a

fully settled result.

ANALOG

INPUT

ADC

OUTPUT

FULLY

SETTLED

1/fADC

Figure 83. Asynchronous Step Change in the Analog Input

Table 55 gives some examples of the relationship between the

values in the FS[10:0] bits and the corresponding output data rate

and settling time.

Table 55. Examples of Output Data Rates and the Corresponding Settling

Times for the Sinc4 Filter

Power Mode

FS[10:0]

Output Data Rate

(SPS)

Settling Time

(ms)

Full Power (fCLK =

614.4 kHz)

1920

400.15

384

80.15

320

66.82

Mid Power (fCLK =

153.6 kHz)

480

400.61

80.61

67.28

Low Power (fCLK =

76.8 kHz)

240

401.22

81.22

67.89

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