ADFS7124-8BBCPZ datasheet(63/93 Pages) AD

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Data Sheet

ADFS7124-8

DIGITAL FILTER

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Rev. 0 | 63 of 93

for each conversion is also the settling time, but the dead time is

reduced to 30.

50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter

Figure 106 shows the frequency response when FS[10:0] is set to

24 in the full power mode, or 6 in the mid power mode or low power

mode. Table 60 lists the corresponding output data rate.

The sinc filter places the first notch at:

fNOTCH = fCLK/(32 × FS[10:0])

The averaging block places notches at fNOTCH/Avg (Avg equaling 16

for the full power mode and mid power mode, and equaling 8 for

the low power mode). Notches are also placed at multiples of this

frequency; therefore, when FS[10:0] is set to 24 in the full power

mode or 6 in the mid power mode, a notch is placed at 800 Hz

due to the sinc filter, and notches are placed at 50 Hz and multiples

of 50 Hz due to the averaging. In the low power mode, a notch is

placed at 400 Hz due to the sinc filter when FS[10:0] is set to 6,

and notches are placed at 50 Hz and multiples of 50 Hz due to the

averaging.

The notch at 50 Hz is a first-order notch; therefore, the notch is

not wide. This means that the rejection at 50 Hz exactly is good,

assuming a stable controllerclock. However, in a band of 50 Hz ±

1 Hz, the rejection degrades significantly. The rejection at 50 Hz ±

0.5 Hz is 40 dB minimum, assuming a stable clock; therefore, a

good controller clock source is recommended when using the fast

settling mode.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 106. 50 Hz Rejection

Figure 107 shows the filter response when FS[10:0] is set to 20 in

the full power mode, or 5 in the mid power and low power modes.

In this case, a notch is placed at 60 Hz and multiples of 60 Hz. The

rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 107. 60 Hz Rejection

Simultaneous 50 Hz/60 Hz rejection is achieved when FS[10:0] is

set to 120 in the full power mode, or 30 in the mid power and

low power modes. Notches are placed at 10 Hz and multiples of

10 Hz, thereby giving simultaneous 50 Hz and 60 Hz rejection. The

rejection at 50 Hz ± 0.5 Hz and 60 Hz ± 0.5 Hz is 42 dB typically.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 108. Simultaneous 50 Hz and 60 Hz Rejection

POST FILTERS

The post filters provide rejection of 50 Hz and 60 Hz simultaneously

and allow the user to trade off settling time and rejection. These

filters can operate up to 27.27 SPS or can reject up to 90 dB of 50

Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized

by post filtering the output of the sinc3 filter. The filter bits must be

set to all 1s to enable the post filter. The post filter option is selected

using the POST_FILTER bits in the filter register. In Figure 109, the

blocks shown in gray are unused.

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