ADFS7124-8BBCPZ datasheet(70/93 Pages) AD

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Data Sheet

ADFS7124-8

DIAGNOSTICS

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Rev. 0 | 70 of 93

result in the MCLK_COUNT register. The MCLK_COUNT register

wraps around after it reaches its maximum value.

Note that the incrementation of the register is asynchronous to

the register read. If a register read coincides with the register

incrementation, it is possible to read an invalid value. To prevent

this, read the register four times rather than once, then read the

possible to identify the correct register value at the start and at the

end of the timing instants.

SPI SCLK COUNTER

The SPI SCLK counter counts the number of SCLK pulses used in

each read and write operation. CS must frame every read and write

operation when this function is used. All read and write operations

are multiples of eight SCLK pulses (8, 16, 32, 40, 48). If the SCLK

counter counts the SCLK pulses and the result is not a multiple

of eight, an error is flagged; the SPI_SCLK_CNT_ERR bit in the

error register is set. If a write operation is being performed and

the SCLK contains an incorrect number of SCLK pulses, the value

is not written to the addressed register and the write operation is

aborted.

The SCLK counter is enabled by setting the SPI_SCLK_

CNT_ERR_EN bit in the ERROR_EN register.

SPI READ/WRITE ERRORS

Along with the SCLK counter, the ADFS7124-8 can also check

the read and write operations to ensure that valid registers are

being addressed. When the SPI_READ_ERR_EN bit or the SPI_

WRITE_ERR_EN bit in the ERROR_EN register are set, the

ADFS7124-8 checks the address of the read/write operations. If

there is an attempt to write to or read from any register other than

the user registers described in this data sheet, an error is flagged;

the SPI_READ_ERR bit or the SPI_WRITE_ERR bit in the error

This function, along with the SCLK counter and the CRC, makes

the serial interface more robust. Invalid registers are not written to

or read from. An incorrect number of SCLK pulses can cause the

serial interface to go asynchronous and incorrect registers to be

accessed. The ADFS7124-8 protects against these issues via the

diagnostics.

SPI_IGNORE ERROR

At certain times, the on-chip registers are not accessible. For

example, during power-up, the on-chip registers are set to their

default values. Wait until this operation is complete before writing

to registers. Also, when offset or gain calibrations are being per-

formed, registers cannot be accessed. If writing to registers during

these busy periods, the SPI_IGNORE_ERR flag is set, indicating

that the ADC is busy and the write operation is ignored. The

SPI_IGNORE_ERR flag is cleared when the bit is read. This diag-

nostic is enabled by default. The function can be disabled using the

SPI_IGNORE_ERR_EN bit in the ERROR_EN register.

CHECKSUM PROTECTION

The ADFS7124-8 has a checksum mode that can be used to

improve interface robustness. Using the checksum ensures that

only valid data is written to a register and allows data read from a

the CRC_ERR bit is set in the error register. However, to ensure

that the register write was successful, read back the register and

verify the checksum.

For CRC checksum calculations, the following polynomial is always

used:

x8 + x2 + x + 1

The CRC_ERR_EN bit in the ERROR_EN register enables and

disables the checksum.

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction is

calculated using the 8-bit command word and the 8-bit to 24-bit

data. For a read transaction, the checksum is calculated using the

command word and the 8-bit to 32-bit data output. Figure 122 and

Figure 123 show SPI write and read transactions, respectively.

8-BIT COMMAND

8-BIT CRC

UP TO 24-BIT INPUT

DATA

CRC

DIN

SCLK

Figure 122. SPI Write Transaction with CRC

8-BIT COMMAND

8-BIT CRC

UP TO 32-BIT OUTPUT

CMD

DATA

CRC

DIN

SCLK

DOUT/

RDY

Figure 123. SPI Read Transaction with CRC

If checksum protection is enabled when continuous read mode is

active, there is an implied command of 0x99 before every data

transmission that must be accounted for when calculating the

checksum value. This ensures a nonzero checksum value even if

the ADC data equals 0x000000.

MEMORY MAP CHECKSUM PROTECTION

For added robustness, a CRC calculation is performed on the

on-chip registers as well. The status register, data register, error

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