ADFS7124-8BBCPZ datasheet(82/93 Pages) AD

82 / 93 page

Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Rev. 0 | 82 of 93

Table 66. ADC Control Register Bit Descriptions (Continued)

Bits

Bit Name

Description

DATA_STATUS

This bit enables the transmission of the status register contents after each data register read. When DATA_STATUS is set, the

contents of the status register are transmitted along with each data register read. This function is useful when several channels are

selected because the status register identifies the channel to which the data register value corresponds.

CS_EN

This bit controls the operation of the DOUT/RDY pin during read operations.

When CS_EN is cleared, the DOUT pin returns to being a RDY pin within nanoseconds of the SCLK inactive edge (the delay is

determined by the DOUT_RDY_DEL bit).

When set, the DOUT/RDY pin continues to output the LSB of the register being read until CS is taken high. CS must frame all

read operations when CS_EN is set. CS_EN must be set to use the diagnostic functions SPI_WRITE_ERR, SPI_READ_ERR, and

SPI_SCLK_CNT_ERR.

REF_EN

Internal reference voltage enable. When this bit is set, the internal reference is enabled and available at the REFOUT pin. When

this bit is cleared, the internal reference is disabled.

7:6

POWER_MODE

Power Mode Select. These bits select the power mode. The current consumption and output data rate ranges are dependent on the

power mode.

00 = low power.

01 = mid power.

10 = full power.

11 = full power.

5:2

Mode

These bits control the mode of operation for ADC. See Table 67.

1:0

CLK_SEL

These bits select the clock source for the ADC. Either the on-chip 614.4 kHz clock can be used or an external clock can be used.

The ability to use an external clock allows several ADFS7124-8 devices to be synchronized. Also, 50 Hz and 60 Hz rejection is

improved when an accurate external clock drives the ADC.

00 = internal 614.4 kHz clock. The internal clock is not available at the CLK pin.

01 = internal 614.4 kHz clock. This clock is available at the CLK pin.

10 = external 614.4 kHz clock.

11 = external clock. The external clock is divided by 4 within the ADFS7124-8.

Table 67. Operating Modes

Mode Value Description

0000

Continuous conversion mode (default). In the continuous conversion mode, the ADC continuously performs conversions and places the result in the data

register. RDY goes low when a conversion is complete. Read these conversions by placing the device in the continuous read mode, whereby the conversions

are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, instruct the ADC to output the conversion by writing to the

communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid

conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice.

0001

Single conversion mode. When the single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The

conversion requires the complete settling time of the filter. The conversion result is placed in the data register, RDY goes low, and the ADC returns to the standby

mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed.

0010

Standby mode. In the standby mode, all sections of the ADFS7124-8 can be powered down except the LDOs. The internal reference, on‑chip oscillator, low-side

power switch, and bias voltage generator can be enabled or disabled while in the standby mode. The on‑chip registers retain their contents in the standby mode.

Any enabled diagnostics remain active when the ADC is in the standby mode. The diagnostics can be enabled/disabled while in the standby mode. However, any

diagnostics that require the controller clock (reference detect, undervoltage/overvoltage detection, LDO trip tests, memory map CRC, and MCLK counter) must

be enabled when the ADC is in the continuous conversion mode or idle mode; these diagnostics do not function if enabled in the standby mode.

0011

Power-down mode. In the power-down mode, all the ADFS7124-8 circuitry is powered down, including the current sources, power switch, burnout currents, bias

voltage generator, and clock circuitry. The LDOs are also powered down. In the power-down mode, the on-chip registers do not retain their contents. Therefore,

coming out of power-down mode, all registers must be reprogrammed.

0100

Idle mode. In the idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided.

0101

Internal zero-scale (offset) calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low

when the calibration is complete. The ADC is placed in the idle mode following a calibration. The measured offset coefficient is placed in the offset register of the

selected channel. Select only one channel when zero-scale calibration is being performed. An internal zero-scale calibration takes a time of one settling period to

be performed.

0110

Internal full-scale (gain) calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration. RDY goes high when

the calibration is initiated and returns low when the calibration is complete. The ADC is placed in the idle mode following a calibration. The measured full-scale

coefficient is placed in the gain register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the

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