ADFS7124-8BBCPZ datasheet(53/93 Pages) AD

53 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 53 of 93

Data=0.75×VIN

VREF ×223−(Offset−0x800000) ×

Gain

0x400000+0x800000

(2)

To start a calibration, write the relevant value to the mode bits in the

ADC_CONTROL register. The DOUT/RDY pin and the RDY bit in

the status register go high when the calibration initiates. When the

calibration is complete, the contents of the corresponding offset or

gain register are updated, the RDY bit in the status register is reset,

the DOUT/RDY pin returns low (if CS is low), and the ADFS7124-8

reverts to the idle mode.

During an internal offset calibration, the selected positive analog

input pin is disconnected, and it is connected internally to the

selected negative analog input pin. So, it is necessary to ensure

that the voltage on the selected negative analog input pin does

not exceed the allowed limits and is free from excessive noise and

interference.

To perform an internal full-scale calibration, a full-scale input volt-

age is automatically connected to the selected analog input for

this calibration. A full-scale calibration is recommended each time

the gain of a channel is changed to minimize the full-scale error.

When performing internal calibrations, the internal full-scale calibra-

tion must be performed before the internal zero-scale calibration.

Therefore, write the value 0x800000 to the offset register before

performing the internal full-scale calibration, which ensures that the

offset register is at its default value. The ADFS7124-8 is factory

calibrated at a gain of 1, and the resulting gain coefficient is the

default gain coefficient on the device. The device does not support

further internal full-scale calibrations at a gain of 1.

System calibrations expect the system zero-scale (offset) and sys-

tem full-scale (gain) voltages to be applied to the ADC pins before

initiating the calibration modes. As a result, errors external to the

ADC are removed. The system zero-scale calibration must be

performed before the system full-scale calibration.

From an operational point of view, treat a calibration like another

ADC conversion. Set the system software to monitor the RDY bit in

the status register or the DOUT/RDY pin to determine the end of a

calibration through a polling sequence or an interrupt-driven routine.

An internal/system offset calibration and system full-scale calibra-

tion requires a time equal to the settling time of the selected filter

to be completed. The internal full-scale calibration requires a time

equal to four settling periods (gain > 1).

A calibration can be performed at any output data rate. Using

lower output data rates results in better calibration accuracy and is

accurate for all output data rates. A new calibration is required for a

given channel if the reference source or the gain for that channel is

changed.

Offset and system full-scale calibrations can be performed in any

power mode. Internal full-scale calibrations can be performed in the

low power or mid power modes only. Thus, when using the full

power mode, select the mid power or low power mode to perform

the internal full-scale calibration. However, an internal full-scale

calibration performed in the low power or mid power mode is valid

in the full power mode, if the same gain is used.

The offset error is typically ±15 µV for gains of 1 to 8 and ±200/

gain µV for higher output data rates. An internal or system offset

calibration reduces the offset error to the order of the noise. The

gain error is factory calibrated at ambient temperature and at a

gain of 1. Following this calibration, the gain error is ±0.0025%

maximum. Therefore, internal full-scale calibrations at a gain of

1 are not supported on the ADFS7124-8. For other gains, the

gain error is −0.3%. An internal full-scale calibration at ambient

temperature reduces the gain error to ±0.016% maximum for gains

of 2 to 8 and ±0.025% typically for higher gains. A system full-scale

calibration reduces the gain error to the order of the noise.

The ADFS7124-8 provides access to the on-chip calibration regis-

ters, allowing the microprocessor to read the calibration coefficients

of the device and to write its own calibration coefficients from

pre-stored values in the EEPROM. A read or write of the offset

and gain registers can be performed at any time except during an

internal or self-calibration. The values in the calibration registers

are 24 bits wide. The span and offset of the device can also be

manipulated using the registers.

SPAN AND OFFSET LIMITS

Whenever a system calibration mode is used, the amount of offset

and span that can be accommodated is limited. The overriding

requirement in determining the amount of offset and gain that can

be accommodated by the device is the requirement that the positive

full-scale calibration limit is ≤1.05 × VREF/gain. This allows the input

range to go 5% above the nominal range. The built-in headroom

in the ADFS7124-8 analog modulator ensures that the device still

operates correctly with a positive full-scale voltage, which is 5%

beyond the nominal.

The range of input span in both the unipolar and bipolar modes has

a minimum value of 0.8 × VREF/gain and a maximum value of 2.1

× VREF/gain. However, the span, which is the difference between

the bottom of the ADFS7124-8 input range and the top of its input

range, must account for the limitation on the positive full-scale

voltage. The amount of offset that can be accommodated depends

on whether the unipolar or bipolar mode is being used. The offset

must account for the limitation on the positive full-scale voltage.

In the unipolar mode, there is considerable flexibility in handling

negative (with respect to AINM) offsets. In both the unipolar and

bipolar modes, the range of positive offsets that can be handled by

the device depends on the selected span. Therefore, in determining

the limits for system zero-scale and full-scale calibrations, ensure

that the offset range plus the span range does exceed 1.05 ×

VREF/gain. This is best illustrated by looking at a few examples.

If the device is used in the unipolar mode with a required span of

0.8 × VREF/gain, the offset range that the system calibration can

handle is from −1.05 × VREF/gain to +0.25 × VREF/gain. If the device

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