ADFS7124-8BBCPZ datasheet(60/93 Pages) AD

60 / 93 page

Data Sheet

ADFS7124-8

DIGITAL FILTER

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Rev. 0 | 60 of 93

When the output data rate is 10 SPS with zero latency disabled

or 3.33 SPS with zero latency enabled, simultaneous 50 Hz and

60 Hz rejection is obtained. The sinc3 filter has rejection of 100 dB

minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz (see Figure 95).

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 95. Sinc3 Filter Response (10 SPS Output Data Rate, Zero Latency

Disabled or 3.33 SPS Output Data Rate, Zero Latency Enabled)

Simultaneous 50 Hz and 60 Hz rejection can also be achieved

using the REJ60 bit in the filter register. When the sinc filter places

a notch at 50 Hz, the REJ60 bit places a first order notch at 60

Hz. The output data rate is 50 SPS when zero latency is disabled

and 16.67 SPS when zero latency is enabled. Figure 96 shows

the frequency response of the sinc3 filter with this configuration.

Assuming a stable clock, the rejection at 50 Hz and 60 Hz (±1 Hz)

is in excess of 67 dB minimum.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

100

125

150

FREQUENCY (Hz)

Figure 96. Sinc3 Filter Response (50 SPS Output Data Rate, Zero Latency

Disabled or 16.67 SPS Output Data Rate, Zero Latency Enabled, REJ60 = 1)

FAST SETTLING MODE (SINC4 + SINC1 FILTER)

In the fast settling mode, the settling time is close to the inverse of

the first filter notch; therefore, it is possible to achieve 50 Hz and/or

60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.

The settling time is approximately equal to 1/output data rate.

Therefore, the conversion time is near constant when converting on

a single channel or when converting on several channels.

Enable the fast settling mode using the filter bits in the filter register.

In the fast settling mode, a sinc1 filter is included after the sinc4

filter. The sinc1 filter averages by 16 in the full power and mid power

modes, and averages by 8 in the low power mode. In Figure 97, the

blocks shown in gray are unused.

SINC3/SINC4

FILTER

MODULATOR

AVERAGING

BLOCK

POST

FILTER

Figure 97. Fast Settling Mode, Sinc4 + Sinc1 Filter

Output Data Rate and Settling Time, Sinc4 +

Sinc1 Filter

When continuously converting on a single channel, the output data

rate is:

fADC = fCLK/(Avg × 32 × FS[10:0])

where:

fADC is the output data rate.

fCLK is the controllerclock frequency (614.4 kHz in full power mode,

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

Avg is 16 for the full or mid power mode and 8 for low power mode.

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the filter

When another channel is selected, there is an extra delay in the

first conversion. The settling time is equal to:

tSETTLE = ((4 + Avg − 1) × 32 × FS[10:0] + Dead Time)/fCLK

where, Dead Time = 95.

Table 59 lists sample FS[10:0] settings and the corresponding

output data rates and settling times.

Table 59. Examples of Output Data Rates and the Corresponding Settling

Times (Fast Settling Mode, Sinc4 + Sinc1)

Power Mode

FS[10:0]

First

Notch

(Hz)

Output Data

Rate (SPS)

Settling

Time (ms)

Full Power (fCLK =

614.4 kHz, Average by

16)

120

118.9

23.9

19.94

Mid Power (fCLK =

153.6 kHz, Average by

16)

119.36

24.36

20.4

Low Power (fCLK =

76.8 kHz, Average by

138.72

28.72

24.14

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