ADFS7124-8BBCPZ datasheet(69/93 Pages) AD

69 / 93 page

Data Sheet

ADFS7124-8

DIAGNOSTICS

analog.com

Rev. 0 | 69 of 93

Figure 119. Analog Input Overvoltage/Undervoltage Monitors

The positive (AINP) and negative (AINM) analog inputs can

be separately checked for overvoltages and undervoltages.

The AINP_OV_ERR_EN and AINP_UV_ERR_EN bits in the ER-

ROR_EN register enable the overvoltage/undervoltage diagnos-

tics respectively. An overvoltage is flagged when the voltage on

AINP exceeds AVDD, while an undervoltage is flagged when the

voltage on AINP goes below AVSS. Similarly, an overvoltage/un-

dervoltage check on the negative analog input pin is enabled

using the AINM_OV_ERR_EN and AINM_UV_ ERR_EN bits in

the ERROR_EN register. The error flags are AINP_OV_ERR,

AINP_UV_ERR, AINM_OV_ERR, and AINM_UV_ERR in the error

When this function is enabled, the corresponding flags may be set

in the error register. Therefore, read the error register when the

overvoltage/undervoltage checks are enabled to ensure that the

flags are reset to 0.

POWER SUPPLY MONITORS

Along with converting external voltages, the ADC can monitor the

voltage on the AVDD pin and the IOVDD pin. When the inputs of

AVDD to AVSS or IOVDD to DGND are selected, the voltage (AVDD

to AVSS or IOVDD to DGND) is internally attenuated by 6, and the

resulting voltage is applied to the Σ-Δ modulator. This is useful

because variations in the power supply voltage can be monitored.

LDO MONITORING

There are several LDO checks included on the ADFS7124-8. Like

the external power supplies, the voltage generated by the analog

and digital LDOs are selectable as inputs to the ADC. In addition,

the ADFS7124-8 can continuously monitor the LDO voltages.

Power Supply Monitor

The voltage generated by the ALDO and DLDO can be

monitored by enabling the ALDO_PSM_ERR_EN bit and the

DLDO_PSM_ERR_EN bit, respectively, in the ERROR_EN regis-

ter. When enabled, the output voltage of the LDO is continuous-

ly monitored. If the ALDO voltage drops below 1.6 V, the AL-

DO_PSM_ERR flag is asserted. If the DLDO voltage drops below

1.55 V, the DLDO_PSM_ERR flag is asserted. The bit remains set

until the corresponding LDO voltage recovers. However, the bit is

only cleared when the error register is read.

1.6V

OVERVOLTAGE

COMPARATOR

ALDO

SET IF ALDO OUTPUT VOLTAGE IS

LESS THAN 1.6V

Figure 120. Analog LDO Monitor

1.55V

OVERVOLTAGE

COMPARATOR

DLDO

SET IF DLDO OUTPUT VOLTAGE IS

LESS THAN 1.55V

Figure 121. Digital LDO Monitor

The ADFS7124-8 can also test the circuitry used for the pow-

er supply monitoring. When the ALDO_PSM_TRIP_TEST_EN or

DLDO_PSM_TRIP_TEST_EN bits are set, the input to the test

circuitry is tied to GND rather than the LDO output. Set the corre-

sponding ALDO_PSM_ERR or DLDO_PSM_ERR bit.

LDO Capacitor Detect

The analog and digital LDOs require an external decoupling capac-

itor of 0.1 µF. The ADFS7124-8 can check for the presence of

this decoupling capacitor. Using the LDO_CAP_CHK bits in the

ERROR_EN register, the LDO being checked is turned off and the

voltage at the LDO output is monitored. If the voltage falls, this is

considered a fail and the LDO_CAP_ERR bit in the error register is

set. Note that a missing decoupling capacitor can cause the ADC

to reset. However, this is easily detectable at the system level by

reading back registers.

Only the analog LDO or digital LDO can be tested for the presence

of the decoupling capacitor at any one time. This test also interferes

with the conversion process.

The circuitry used to check for missing decoupling capacitors

can also be tested by the ADFS7124-8. When the LDO_CAP_

CHK_TEST_EN bit in the ERROR_EN register is set, the decou-

pling capacitor is internally disconnected from the LDO, forcing

a fault condition. Therefore, when the LDO capacitor test is per-

formed, a fault condition is reported, that is, the LDO_CAP_ERR bit

in the error register is set.

MCLK COUNTER

A stable controller clock is important as the output data rate, filter

settling time, and the filter notch frequencies are dependent on the

controller clock. The ADFS7124-8 allows to monitor the controller

clock. When the MCLK_CNT_EN bit in the ERROR_EN register

is set, the MCLK_COUNT register increments by 1 every 131

controller clock cycles. Monitor this register over a fixed period of

time. The controller clock frequency can be determined from the

ADFS7124-8BBCPZ датащи(PDF) 69 Page - Analog Devices

ADFS7124-8BBCPZ датащи(HTML) 69 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

датащи скачать

ссылки URL