ADFS7124-8BBCPZ datasheet(14/93 Pages) AD

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Data Sheet

ADFS7124-8

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 14 of 93

Figure 9. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

REGCAPD

Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 µF capacitor.

IOVDD

Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOVDD is independent of AVDD. Therefore, the serial interface can operate at 1.65 V

with AVDD at 3.6 V, for example.

DGND

Digital Ground Reference Point.

AIN0/IOUT/VBIAS

Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT1 or IOUT0 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN1/IOUT/VBIAS

Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN2/IOUT/VBIAS/P1

Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This input pin is configured

through the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the

internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this

output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

AIN3/IOUT/VBIAS/P2

Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This input pin is configured

through the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the

internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this

output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

AIN4/IOUT/VBIAS/P3

Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 3. This input pin is configured

through the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the

internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this

output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

AIN5/IOUT/VBIAS/P4

Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 4. This input pin is configured

through the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the

internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this

output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

AIN6/IOUT/VBIAS

Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN7/IOUT/VBIAS

Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

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