ADFS7124-8BBCPZ datasheet(88/93 Pages) AD

88 / 93 page

Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Table 71. ERROR_EN Register Bit Descriptions (Continued)

Bits

Bit Name

Description

SPI_READ_ERR_EN

When this bit is set, the SPI_READ_ERR bit in the error register is set when an error occurs during a read operation. An

error occurs if there is an attempt to read from invalid addresses.CS_EN in the ADC_CONTROL register must be set to 1

when the SPI read check function is being used.

SPI_WRITE_ERR_EN

When this bit is set, the SPI_WRITE_ERR bit in the error register is set when an error occurs during a write operation.

An error occurs if there is an attempt to write to invalid addresses or write to read-only registers. CS_EN in the

ADC_CONTROL register must be set to 1 when the SPI write check function is being used.

SPI_CRC_ERR_EN

This bit enables a CRC check of all read and write operations. The SPI_CRC_ERR bit in the error register is set if the CRC

check fails. In addition, an 8-bit CRC word is appended to all data read from the ADFS7124-8.

MM_CRC_ERR_EN

When this bit is set, a CRC calculation is performed on the memory map each time that the registers are written to.

Following this, periodic CRC checks are performed on the on-chip registers. If the register contents have changed, the

MM_CRC_ERR bit is set.

ROM_CRC_ERR_EN

When this bit is set, a CRC calculation is performed on the ROM contents on power-on. If the ROM contents have

changed, the ROM_CRC_ERR bit is set.

MCLK_COUNT REGISTER

RS[5:0] = 0, 0, 1, 0, 0, 0

Power-On/Reset = 0x00

The controller clock frequency can be monitored using this register.

Table 72 outlines the bit designations for the register. Bit 7 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCLK_COUNT (0)

Table 72. MCLK_COUNT Register Bit Descriptions

Bits

Bit Name

Description

7:0

MCLK_COUNT

This register allows the user to determine the frequency of the internal/external oscillator. Internally, a clock counter increments every 131

pulses of the sampling clock (614.4 kHz in the full power mode, 153.6 kHz in the mid power mode, and 768 kHz in the low power mode). The

8-bit counter wraps around on reaching its maximum value. The counter output is read back through this register.

Note that the incrementation of the register is asynchronous to the register read. If a register read coincides with the register incrementation, it

is possible to read an invalid value. To prevent this, read the register four times rather than once, then read the register four times again at a

later point. By reading four values, it is possible to identify the correct register value at the start and at the end of the timing instants.

CHANNEL REGISTERS

RS[5:0] = 0, 0, 1, 0, 0, 1 to 0, 1, 1, 0, 0, 0

Power-On/Reset = 0x8001 for CHANNEL_0; all other channel registers are set to 0x0001

Sixteen channel registers are included on the ADFS7124-8, CHANNEL_0 to CHANNEL_15. The channel registers begin at Address 0x09

(CHANNEL_0) and end at Address 0x18 (CHANNEL_15). Through each register, configure the channel (AINP input and AINM input), enable

or disable the channel, and select the setup. The setup is selectable from eight different options. When the ADC converts, it automatically

sequences through all enabled channels. This allows the user to sample some channels multiple times in a sequence, if required. In addition, it

allows the user to include diagnostic functions in a sequence also.

Table 73 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Enable (1)

Setup (0)

(0)

0 (0)

AINP[4:3] (00)

AINP[2:0] (000)

AINM[4:0] (00001)

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