ADFS7124-8BBCPZ datasheet(92/93 Pages) AD

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Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Rev. 0 | 92 of 93

Table 75. Filter Register Bit Descriptions (Continued)

Bits

Bit Name

Description

011 = reserved.

100 = fast settling filter using the sinc4 filter. The sinc4 filter is followed by an averaging block, which results in a settling time equal to

the conversion time. In full power and mid power modes, averaging by 16 occurs whereas averaging by 8 occurs in low power mode.

101 = fast settling filter using the sinc3 filter. The sinc3 filter is followed by an averaging block, which results in a settling time equal to

the conversion time. In full power and mid power modes, averaging by 16 occurs whereas averaging by 8 occurs in low power mode.

110 = reserved.

111 = post filter enabled. The ADFS7124-8 includes several post filters, selectable using the POST_FILTER bits. The post filters have

single cycle settling, the settling time being considerably better than a simple sinc3/sinc4 filter. These filters offer excellent 50 Hz and

60 Hz rejection.

REJ60

When this bit is set, a first order notch is placed at 60 Hz when the first notch of the sinc filter is at 50 Hz. This allows simultaneous 50

Hz and 60 Hz rejection.

19:17

POST_FILTER

Post filter type select bits. When the filter bits are set to 1, the sinc3 filter is followed by a post filter that offers good 50 Hz and 60 Hz

rejection at output data rates that have zero latency approximately.

POST_FILTER

Output Data Rate (SPS)

Rejection at 50 Hz and 60 Hz ± 1 Hz (dB)

000

Reserved

Not applicable

010

Reserved

Not applicable

010

27.27

011

100

Reserved

Not applicable

101

110

16.7

111

Reserved

Not applicable

SINGLE_CYCLE

Single cycle conversion enable bit. When this bit is set, the ADFS7124-8 settles in one conversion cycle so that it functions as a zero

latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected.

When the fast filters are used, this bit has no effect.

15:11

These bits must be programmed with a Logic 0 for correct operation.

10:0

FS[10:0]

Filter output data rate select bits. These bits set the output data rate of the sinc3 filter, sinc4 filter, and fast settling filters. In addition,

they affect the position of the first notch of the sinc filter and the cutoff frequency. In association with the gain selection, they also

determine the output noise and, therefore, the effective resolution of the device (see noise tables). FS can have a value from 1 to

2047.

OFFSET REGISTERS

RS[5:0] = 1, 0, 1, 0, 0, 1 to 1, 1, 0, 0, 0, 0

Power-On/Reset = 0x800000

The ADFS7124-8 has eight offset registers, OFFSET_0 to OFFSET_7. Each offset register is associated with a setup; OFFSET_x is associated

with Setup x. The offset registers are 24-bit registers and hold the offset calibration coefficient for the ADC and its power-on reset value is

0x800000. Each of these registers is a read/write register. These registers are used in conjunction with the associated gain register to form a

register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated. The ADC must be

placed in the standby mode or idle mode when writing to the offset registers.

GAIN REGISTERS

RS[5:0] = 1, 1, 0, 0, 0, 1 to 1, 1, 1, 0, 0, 0

Power-On/Reset = 0x5XXXXX

The ADFS7124-8 has eight gain registers, GAIN_0 to GAIN_7. Each gain register is associated with a setup; GAIN_x is associated with Setup

x. The gain registers are 24-bit registers and hold the full-scale calibration coefficient for the ADC. The ADFS7124-8 is factory calibrated

to a gain of 1. The gain register contains this factory generated value on power-on and after a reset. The gain registers are read/write

registers. However, when writing to the registers, the ADC must be placed in the standby mode or idle mode. The default value is automatically

overwritten if an internal or system full-scale calibration is initiated or the full-scale registers are written to.

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