ADFS7124-8BBCPZ datasheet(47/93 Pages) AD

47 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 47 of 93

PROGRAMMABLE GAIN AMPLIFIER (PGA)

When the gain stage is enabled, the output from the multiplexer

is applied to the input of the PGA. The presence of the PGA

means that signals of small amplitude can be gained within the

ADFS7124-8 and still maintain excellent noise performance.

BUF

ANALOG

BUFFERS

PGA2

PGA1

24-BIT

Σ-Δ ADC

Figure 74. Programmable Gain Amplifier (PGA)

The ADFS7124-8 can be programmed to have a gain of 1, 2, 4,

8, 16, 32, 64, or 128 by using the PGA bits in the configuration

of 1, both stages are bypassed. For gains of 2 to 8, a single stage is

used, whereas for gains greater than 8, both stages are used.

The analog input range is ±VREF/gain. Therefore, with an external

2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to

0 V to 2.5 V, and the bipolar ranges are from ±19.53 mV to ±2.5

V. For high reference values, for example, VREF = AVDD, the analog

input range must be limited. Consult the Specifications section for

more details on these limits.

REFERENCE

The ADFS7124-8 has an embedded 2.5 V reference. The embed-

ded reference is a low noise, low drift reference with 15 ppm/°C

drift maximum. Including the reference on the ADFS7124-8 reduces

the number of external components needed in applications such as

thermocouples, leading to a reduced PCB size.

BAND GAP

REF

24-BIT

Σ-Δ ADC

REFIN1(+)

REFOUT

REFIN1(–)

REFIN2(+)

REFIN2(–)

AVDD

AVSS

REFERENCE

BUFFERS

Figure 75. Reference Connections

This reference can be used to supply the ADC (by setting the

REF_EN bit in the ADC_CONTROL register to 1) or an external

reference can be applied. For external references, the ADC has

a fully differential input capability for the channel. In addition, the

user can select one of two external reference options (REFIN1 or

REFIN2). The reference source for the ADFS7124-8 is selected

using the REF_SEL bits in the configuration register (see Table 49).

When the internal reference is selected, it is internally connected to

the modulator. It can also be made available on the REFOUT pin.

A 0.1 µF decoupling capacitor is required on REFOUT when the

internal reference is active.

The common-mode range for the differential reference inputs is

from AVSS − 50 mV to AVDD + 50 mV when the reference buffers

are disabled. The reference inputs can also be buffered on-chip.

The buffers require 100 mV of headroom. The reference voltage

of REFIN (REFINx(+) − REFINx(−)) is 2.5 V nominal, but the

ADFS7124-8 is functional with reference voltages from 0.5 V to

AVDD.

In applications where the excitation (voltage or current) for the

transducer on the analog input also drives the reference voltage for

the devices, the effect of the low frequency noise in the excitation

source is removed, because the application is ratiometric. If the

ADFS7124-8 is used in nonratiometric applications, use a low noise

reference.

The recommended 2.5 V reference voltage sources for the

ADFS7124-8 include the ADR4525, which is a low noise, low power

reference. Note that the reference input provides a high impedance,

dynamic load when unbuffered. Because the input impedance of

each reference input is dynamic, resistor/capacitor combinations

on these inputs can cause DC gain errors if the reference inputs

are unbuffered, depending on the output impedance of the source

driving the reference inputs.

Reference voltage sources typically have low output impedances

and are, therefore, tolerant to having decoupling capacitors on

REFINx(+) without introducing gain errors in the system. Deriving

the reference input voltage across an external resistor means that

the reference input sees a significant external source impedance. In

this situation, using the reference buffers is required.

REFINx(+)

1µF

4.7µF

ADR4525

2.5V REF

REFINx(–)

0.1µF

4.7µF

Figure 76. ADR4525 to ADFS7124-8 Connections

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the ADFS7124-8 can accept either unipolar or

bipolar input voltage ranges, which allows the user to tune the ADC

input range to the sensor output range. When a split power supply

is used, the device accepts truly bipolar inputs. When a single

power supply is used, a bipolar input range does not imply that the

device can tolerate negative voltages with respect to system AVSS.

Unipolar and bipolar signals on the AINP input are referenced to

the voltage on the AINM input. For example, if AINM is 1.5 V and

the ADC is configured for unipolar mode with a gain of 1, the input

voltage range on the AINP input is 1.5 V to 3 V when VREF =

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