ADFS7124-8BBCPZ datasheet(45/93 Pages) AD

45 / 93 page

Data Sheet

ADFS7124-8

GETTING STARTED

analog.com

Rev. 0 | 45 of 93

Figure 72 shows an example of how the channel registers span

between the analog input pins and setup configurations down-

stream. In this random example, two differential inputs and two

single-ended inputs are required. The single-ended inputs are the

AIN0/AIN7 and AIN6/AIN7 combinations. The first differential input

pair (AIN0/AIN1) uses Setup 0. The two single-ended input pairs

(AIN0/AIN7 and AIN6/AIN7) are set up as diagnostics; therefore,

they use a separate setup (Setup 1). The final differential input

(AIN2/AIN3) also uses a separate setup: Setup 2.

Given that three setups are selected for use, the CONFIG_0,

CONFIG_1, and CONFIG_2 registers are programmed as required,

and the FILTER_0, FILTER_1, and FILTER_2 registers are also

programmed as required. Optional gain and offset correction can

be employed on a per setup basis by programming the GAIN_0,

GAIN_1, and GAIN_2 registers, and the OFFSET_0, OFFSET_1,

and OFFSET_2 registers.

In the example shown in Figure 72, the CHANNEL_0 to CHAN-

NEL_3 registers are used. Setting the MSB (the enable bit) in each

of these registers enables the four combinations through the cross-

point multiplexer. When the ADFS7124-8 converts, the sequencer

transitions in ascending sequential order from CHANNEL_0 to

CHANNEL_1 to CHANNEL_2, and then on to CHANNEL_3 before

looping back to CHANNEL_0 to repeat the sequence.

CONFIGURATION

REGISTERS

FILTER

REGISTERS

OFFSET

REGISTERS

GAIN

REGISTERS

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT ANALOG INPUT PARTS

ENABLE THE CHANNEL

SELECT SETUP

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

ANALOG INPUT BUFFERS

REFERENCE BUFFERS

BURNOUT

REFERENCE SOURCE

GAIN

SINC4

SINC3

SINC4 + SINC1

SINC3 + SINC1

ENHANCED 50Hz/60Hz REJECTION

GAIN CORRECTION

OPTIONALLY

PROGRAMMED

PER SETUP AS REQUIRED

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

CONFIG_3

CONFIG_5

CONFIG_6

CONFIG_7

CONFIG_4

CONFIG_0

CONFIG_2

CONFIG_1

FILTER_3

FILTER_5

FILTER_6

FILTER_7

FILTER_4

FILTER_0

FILTER_2

FILTER_1

GAIN_3

GAIN_5

GAIN_6

GAIN_7

GAIN_4

GAIN_0

GAIN_2

GAIN_1

OFFSET_3

OFFSET_5

OFFSET_6

OFFSET_7

OFFSET_4

OFFSET_0

OFFSET_2

OFFSET_1

0x09

CHANNEL_0

0x0A

CHANNEL_1

0x0B

CHANNEL_2

0x0C

CHANNEL_3

0x0D

CHANNEL_4

0x0E

CHANNEL_5

0x0F

CHANNEL_6

0x10

CHANNEL_7

CHANNEL_8

CHANNEL_9

CHANNEL_10

CHANNEL_11

CHANNEL_12

CHANNEL_13

CHANNEL_14

CHANNEL_15

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CHANNEL

REGISTERS

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

Figure 72. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups

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