ADFS7124-8BBCPZ datasheet(68/93 Pages) AD

68 / 93 page

Data Sheet

ADFS7124-8

DIAGNOSTICS

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Rev. 0 | 68 of 93

The ADFS7124-8 has numerous diagnostic functions on chip. Use

these features to ensure:

►

Read/write operations are to valid registers only.

►

Only valid data is written to the on-chip registers.

►

Appropriate decoupling is used on the LDOs.

►

The external reference, if used, is present.

►

The ADC modulator and filter are working within specification.

SIGNAL CHAIN CHECK

Functions such as the reference and power supply voltages can

be selected as inputs to the ADC. The ADFS7124-8 can therefore

check the voltages connected to the device. The ADFS7124-8 also

generates an internal 20 mV signal that can be applied internally to

a channel by selecting the V_20MV_P to V_20MV_M channel in the

channel register. The internal 20 mV uses a common-mode voltage

of 10 mV. Therefore, the absolute voltage of V_20MV_M is AVSS.

If the AINM_UV_ERR function is enabled, the AINM_UV_ERR flag

may be set when the internal 20 mV is being measured. So, ignore

the AINM_UV_ERR flag status when converting the internal 20 mV

signal. The PGA can be checked using this function. As the PGA

setting is increased, for example, the signal as a percent of the

analog input range is increased by a factor of two. This allows the

user to check that the PGA is functioning correctly. Note that the

internal 20 mV cannot be used to test the signal chain at a gain

of 1, AIN_BUFM and/or AIN_BUFP buffer enabled as the buffer

requires 100 mV of headroom. To test the signal chain for this

configuration, the power supply or LDO can be selected as the

analog input.

REFERENCE DETECT

The ADFS7124-8 includes on-chip circuitry to detect if there is

a valid reference for conversions or calibrations when selecting

an external reference as the reference source. This is a valuable

feature in applications such as RTDs or strain gages where the

reference is derived externally.

Figure 118. Reference Detect Circuitry

This feature is enabled when the REF_DET_ERR_EN bit in the

ERROR_EN register is set to 1. If the voltage between the selected

REFINx(+) and REFINx(−) pins goes below 0.7 V, or either the

REFINx(+) or REFINx(−) inputs are open circuit, the ADFS7124-8

detects that it no longer has a valid reference. In this case, the

REF_DET_ERR bit in the error register is set to 1. The ERR bit in

the status register is also set.

If the ADFS7124-8 is performing normal conversions and the

REF_DET_ERR bit becomes active, the conversion results revert

to all 1s. Therefore, it is not necessary to continuously monitor the

status of the REF_DET_ERR bit when performing conversions. It is

only necessary to verify its status if the conversion result read from

the ADC data register is all 1s.

If the ADFS7124-8 is performing either offset or full-scale calibra-

tions and the REF_DET_ERR bit becomes active, the updating

of the respective calibration register is inhibited to avoid loading

incorrect coefficients to the register, and the REF_DET_ERR bit is

set. If there is a concern about verifying that a valid reference is in

place every time a calibration is performed, check the status of the

REF_DET_ERR bit at the end of the calibration cycle.

The reference detect flag may be set when the device exits the

standby mode. Therefore, read the error register after exiting the

standby mode to reset the flag to 0.

CALIBRATION, CONVERSION, AND

SATURATION ERRORS

The conversion process and calibration process can also be

monitored by the ADFS7124-8. These diagnostics check the

analog input used as well as the modulator and digital filter

during conversions or calibration. The functions can be ena-

bled using the ADC_CAL_ERR_EN, ADC_CONV_ERR_EN, and

ADC_SAT_ERR_EN bits in the ERROR_EN register. With these

functions enabled, the ADC_ CAL_ERR, ADC_CONV_ERR, and

ADC_SAT_ERR bits are set if an error occurs.

The ADC_CONV_ERR flag is set if there is an overflow or under-

flow in the digital filter. The ADC conversion clamps to all 0s or all

1s also. This flag is updated in conjunction with the update of the

data register and can be cleared only by a read of the error register.

The ADC_SAT_ERR flag is set if the modulator outputs 20 consec-

utive 1s or 0s. This indicates that the modulator has saturated.

When an offset calibration is performed, the resulting offset coeffi-

cient must be between 0x7FFFF and 0xF80000. If the coefficient

is outside this range, the offset register is not updated and the

ADC_CAL_ERR flag is set. During a full-scale calibration, overflow

of the digital filter is checked. If an overflow occurs, the error flag is

set and the gain register is not updated.

OVERVOLTAGE/UNDERVOLTAGE DETECTION

The overvoltage/undervoltage monitors check the absolute voltage

on the AINx analog input pins. The absolute voltage must be within

specification to meet the data sheet specifications. If the ADC is

operated outside the data sheet limits, linearity degrades.

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