ADFS7124-8BBCPZ datasheet(62/93 Pages) AD

62 / 93 page

Data Sheet

ADFS7124-8

DIGITAL FILTER

analog.com

Rev. 0 | 62 of 93

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY (Hz)

120

150

Figure 102. Simultaneous 50 Hz and 60 Hz Rejection

FAST SETTLING MODE (SINC3 + SINC1 FILTER)

In the fast settling mode, the settling time is close to the inverse of

the first filter notch; therefore, it is possible to achieve 50 Hz and/or

60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.

The settling time is approximately equal to 1/output data rate.

Therefore, the conversion time is near constant when converting on

a single channel or when converting on several channels.

Enable the fast settling mode using the filter bits in the filter register.

In the fast settling mode, a sinc1 filter is included after the sinc3

filter. The sinc1 filter averages by 16 in the full power and mid power

modes, and averages by 8 in the low power mode. In Figure 103,

the blocks shown in gray are unused.

SINC3 /SINC4

FILTER

MODULATOR

AVERAGING

BLOCK

POST

FILTER

Figure 103. Fast Settling Mode, Sinc3 + Sinc1 Filter

Output Data Rate and Settling Time, Sinc3 +

Sinc1 Filter

When continuously converting on a single channel, the output data

rate is:

fADC = fCLK/(Avg × 32 × FS[10:0])

where:

fADC is the output data rate.

fCLK is the controller clock frequency (614.4 kHz in full power mode,

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

Avg is 16 in full or mid power mode and 8 in low power mode.

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the filter

When another channel is selected, there is an extra delay in the

first conversion. The settling time is equal to:

tSETTLE = ((3 + Avg − 1) × 32 × FS[10:0] + Dead Time)/fCLK

where, Dead Time = 95.

Table 60 lists some sample FS[10:0] settings and the corresponding

output data rates and settling times.

Table 60. Examples of Output Data Rates and the Corresponding Settling

Times (Fast Settling Mode, Sinc3 + Sinc1)

Power Mode

FS[10:0]

First Notch

(Hz)

Output Data

Rate (SPS)

Settling

Time (ms)

Full Power (fCLK =

614.4 kHz, Average

by 16)

120

112.65

22.65

18.9

Mid Power (fCLK =

153.6 kHz, Average

by 16)

113.11

23.11

19.36

Low Power (fCLK =

76.8 kHz, Average by

126.22

26.22

22.06

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data rate.

CONVERSIONS

CHANNEL A

CHANNEL

CHANNEL B

CH A CH A CH A CH A

CH A

CH B CH B

1/fADC DT/fCLK

NOTES

1. DT = DEAD TIME.

Figure 104. Fast Settling, Sinc3 + Sinc1 Filter

When the device is converting on a single channel and a step

change occurs on the analog input, the ADC does not detect

the change and continues to output conversions. When the step

change is synchronized with the conversion, one intermediate result

is not completely settled (see Figure 105). If the step change is

asynchronous to the conversion process, one or two intermediate

results are not completely settled.

ANALOG

INPUT

ADC

OUTPUT

VALID

fADC

Figure 105. Step Change on the Analog Input, Sinc3 + Sinc1 Filter

Sequencer

The description in the Fast Settling Mode (Sinc3 + Sinc1 Filter)

section is valid when manually switching channels, for example,

writing to the device to change channels. When multiple channels

are enabled, the on-chip sequencer is automatically used; the

device automatically sequences between all enabled channels. In

this case, the first conversion takes the complete settling time, as

listed in Table 60. For all subsequent conversions, the time needed

ADFS7124-8BBCPZ датащи(PDF) 62 Page - Analog Devices

ADFS7124-8BBCPZ датащи(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

датащи скачать

ссылки URL