ADFS7124-8BBCPZ datasheet(10/93 Pages) AD

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Data Sheet

ADFS7124-8

SPECIFICATIONS

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Rev. 0 | 10 of 93

TIMING CHARACTERISTICS

AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, Input Logic 0

= 0 V, Input Logic 1 = IOVDD, unless otherwise noted.

Table 3. Timing Characteristics

Parameter1, 2

Min

Typ

Max

Unit

Test Conditions/Comments

100

SCLK high pulse width

100

SCLK low pulse width

t12

Delay between consecutive read/write operations

3/MCLK3

Full power mode

12/MCLK

Mid power mode

24/MCLK

Low power mode

t13

µs

DOUT/ high time if DOUT/RDY is low and the next conversion is

available

µs

Full power mode

µs

Mid power mode

µs

Low power mode

t14

SYNC low pulse width

3/MCLK

Full power mode

12/MCLK

Mid power mode

24/MCLK

Low power mode

READ OPERATION

CS falling edge to DOUT/RDY active time

t24

SCLK active edge5 to data valid delay

t56, 7

Bus relinquish time after CS inactive edge

SCLK inactive edge to CS inactive edge

t78

SCLK inactive edge to DOUT/RDY high

The DOUT_RDY_DEL bit is cleared, the CS_EN bit is cleared

110

The DOUT_RDY_DEL bit is set, the CS_EN bit is cleared

t7A7

Data valid after CS inactive edge, the CS_EN bit is set

WRITE OPERATION

CS falling edge to SCLK active edge5 setup time

Data valid to SCLK edge setup time

t10

Data valid to SCLK edge hold time

t11

CS rising edge to SCLK edge hold time

1 These specifications were sample tested during the initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of IOVDD and timed

from a voltage level of IOVDD/2.

2 See Figure 3, Figure 4, Figure 5, and Figure 6.

3 MCLK is the controller clock frequency.

4 These specifications are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

5 The SCLK active edge is the falling edge of SCLK.

6 These specifications are derived from the measured time taken by the data output to change by 0.5 V when loaded with the circuit shown in Figure 2. The measured

number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. The times quoted in the timing characteristics are the true bus

relinquish times of the device and, therefore, are independent of external bus loading capacitances.

7 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,

although subsequent reads must not occur close to the next output update. In continuous read mode, the digital word can be read only once.

8 When the CS_EN bit is cleared, the DOUT/RDY pin changes from its DOUT function to its RDY function, following the last inactive edge of the SCLK. When CS_EN is set,

the DOUT pin continues to output the LSB of the data until the CS inactive edge.

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