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LPC55S6X датащи(PDF) 100 Page - NXP Semiconductors |
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LPC55S6X датащи(HTML) 100 Page - NXP Semiconductors |
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100 / 128 page ![]() LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.9 — 10 February 2020 100 of 128 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller [1] Characterized on typical samples, not tested in production ; Tamb = 25 °C [2] On device revision 0A, the hysteresis on the comparator cannot be enabled tdelay propagation delay time Low Power Mode negative input = VBAT_DCDC/2 V_overdrive = 10 mV - 1150 6000 ns V_overdrive = 50 mV - 3100 - ns V_overdrive = max - 900 3000 ns propagation delay time Low Power Mode negative input = VBAT_DCDC - 0.1 V V_overdrive = 10 mV - 6000 - ns V_overdrive = 50 mV - 6000 - ns V_overdrive = max - 4400 - ns propagation delay time Low Power Mode negative input = 0.1 V V_overdrive = 10 mV - 2400 - ns V_overdrive = 50 mV - 2300 - ns V_overdrive = max - 50 2000 ns propagation delay time Fast Mode negative input = VBAT_DCDC/2 V_overdrive = 10 mV - 800 2000 ns V_overdrive = 50 mV - 520 - ns V_overdrive = max - 210 300 ns propagation delay time Fast Mode negative input = VBAT_DCDC - 0.1 V V_overdrive = 10 mV - 1600 - ns V_overdrive = 50 mV - 1150 - ns V_overdrive = max - 790 - ns propagation delay time Fast Mode negative input = 0.1 V V_overdrive = 10 mV - 1400 - ns V_overdrive = 50 mV - 405 - ns V_overdrive = max - 40 100 ns Vhys [2] hysteresis voltage (VHYST_P - VHSYT_N) Common Mode Input Voltages in [200 mV: Vbat - 200mV] range (See Vin_N in Figure 22) - 100 200 mV Rlad ladder resistance Resistive ladder, Divider ratio programmed with 5-bit control word. Entry point is either PIO1_19 or internal VBAT_PMU -1.27 - M Fig 22. Comparator Hysteresis Table 40. Comparator characteristics …continued Tamb = 40 C to +105 C unless noted otherwise; VBAT_PMU = 1.8 V to 3.6 V. Symbol Parameter Conditions Min Typ[1] Max Unit |
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