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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC55S6X датащи(PDF) 94 Page - NXP Semiconductors |
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LPC55S6X датащи(HTML) 94 Page - NXP Semiconductors |
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94 / 128 page  LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.9 — 10 February 2020 94 of 128 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller 11.12 USART interface The actual USART bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master and slave synchronous mode is 10 Mbit/s. Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master and slave asynchronous mode is 6.25 Mbit/s. [1] Based on simulated values. Not tested in production. Table 34. USART dynamic characteristics[1] Tamb = 40 C to 105 C; VDD = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = fast-mode for all pins; Parameters sampled at the 50% level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit USART master (in synchronous mode) tsu(D) data input set-up time 6 - - ns th(D) data input hold time 0 - - ns tv(Q) data output valid time 5 - 11 ns USART slave (in synchronous mode) tsu(D) data input set-up time 6 - - ns th(D) data input hold time 0 - - ns tv(Q) data output valid time 9 - 25 ns Fig 19. USART timing Un_SCLK (CLKPOL = 0) TXD RXD Tcy(clk) tsu(D) th(D) tv(Q) START BIT0 tvQ) Un_SCLK (CLKPOL = 1) START BIT0 BIT1 BIT1 aaa-015074 |
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