LPC55S6X datasheet(40/128 Pages) NXP

40 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

40 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7. Functional description

7.1 Architectural overview

The Arm Cortex M33 includes two AHB-Lite buses, one system bus and one code and

bus. The Code AHB (C-AHB) interface is used for any instruction fetch and data access to

the Code region of the ARMv8-M memory map ([0x00000000 - 0x1FFFFFFF]). The

System AHB (S-AHB) interface is used for instruction fetch and data access to all other

regions of the ARMv8-M memory map ([0x20000000 - 0xFFFFFFFF]).

The LPC55S6x uses a multi-layer AHB matrix to connect the ARM Cortex-M33 buses and

other bus masters to peripherals in a flexible manner that optimizes performance by

allowing peripherals that are on different slave ports of the matrix to be accessed

simultaneously by different bus masters. Figure 3 “LPC55S6x Block diagram” shows

details of the available matrix connections.

7.2 Arm Cortex-M33 processor (CPU0)

The ARM Cortex-M33 is based on the ARMv8-M architecture that offers systems

enhancements, such as ARM TrustZone® security, single-cycle digital signal processing,

low power consumption, enhanced debug features, and a high level of support block

integration. The ARM Cortex-M33 CPU employs a 7-stage instruction pipe and includes

an internal prefetch unit that supports speculative branching. A hardware floating-point

processor is integrated into the core. On the LPC55S6x, the Cortex-M33 is augmented

with two hardware co-processors providing accelerated support for additional DSP

algorithms and cryptography.

The Arm Cortex M33 provides a security foundation, offering isolation to protect valuable

IP and data with TrustZone technology. It simplifies the design and software development

of digital signal control systems with the integrated digital signal processing (DSP)

instructions.

7.3 Arm Cortex-M33 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root operations. It also provides conversions between fixed-point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 standard.

7.4 Arm Cortex-M33 (CPU1)

The LPC55S6x device includes a second instance of Cortex-M33. The configuration of

this instance does not include MPU, FPU, DSP, ETM, Trustzone (SECEXT), Secure

Attribution Unit (SAU) or co-processor interface. It supports the same debug levels and

interrupt lines as the primary CPU.

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