LPC55S6X datasheet(68/128 Pages) NXP

68 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

68 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.31.5 PRINCE On-the-fly encryption/decryption

LPC55S6x devices offer support for on-the-fly encryption of date being written to flash and

decryption of encrypted on-chip flash data during read using the PRINCE encryption

algorithm. Compared to AES, PRINCE is fast as it can decrypt and encrypt in one clock

cycle. Also, it does not need extra SRAM to copy data. It operates on a block-size of 64

bits with an 128-bit key. This functionality is useful for asset protection, such as securing

application code, securing stored keys and enabling secure flash update.

7.31.6 Universally Unique Identifier (UUID)

Each LPC55S6x device consists of a unique 128-bit IETF RFC4122 compliant

non-sequential UUID. It can be read from the protected flash region (register location

0x0009_FC70 onwards).

7.32 Debug Mailbox and Authentication

The Debugger Mailbox (DM) AP offers a register based mailbox accessible by both CPUs

and the device debug port DP of the MCU. This port is always enabled and external world

can send and receive data to/from ROM. This port is used to implement NXP Debug

Authentication Protocol.

BootROM implements debug mailbox protocol to interact with tools over SWD interface.

LPC55S6x offers a debug authentication protocol as a tool to authenticate the

debugger and grant it access to the device. The debug authentication scheme on

LPC55S6x is a challenge-response scheme and assures that debugger in

possession of required debug credentials only can successfully authenticate over debug

interface and access restricted parts of the device. This protocol provides a mechanism

for a device and its debug interface to authenticate the identity and credentials of the

debugger (or user). Access right settings can be pre-configured and gets loaded into

is successfully completed, secure part of the device is non-accessible to the debugger.

7.33 Emulation and debugging

Debug and trace functions are integrated into the Arm Cortex-M33 (CPU0 and CPU1)

Serial wire debug and trace function (Serial Wire Output) are supported. Eight breakpoints

and four watch points are supported. In addition, JTAG boundary scan mode is provided.

The Arm SYSREQ reset is supported and causes the processor to reset the peripherals,

execute the boot code, restart from address 0x0000 0000, and break at the user entry

point.

The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the

SWD functions by default.

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