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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC55S6X датащи(PDF) 74 Page - NXP Semiconductors |
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LPC55S6X датащи(HTML) 74 Page - NXP Semiconductors |
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74 / 128 page  LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.9 — 10 February 2020 74 of 128 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller 10.3 Power consumption [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C). Characterized through bench measurements using typical samples. [2] Clock source FRO. PLL disabled [3] Compiler settings: IAR v.8.20.2., optimization level 0, optimized for time off. [4] Flash is powered down [5] PLL enabled [6] For device revision 1B, power library in SDK sets the DCDC output based on the frequency selected. For frequencies 100 MHz or below, DCDC output is set between 1.0 V to 1.075 V, for frequencies between 101 MHz to 130 MHz, DCDC output is set between 1.025 V to 1.150 V and for frequencies above 130 MHz, DCDC output is set between 1.050 V to 1.2 V. For device revision 0A, the default typical DCDC output is 1.1 V and for device revision 1B, the typical default DCDC output is 1.0 V. [7] See the FLASHCFG register in the LPC55S6x User Manual for system clock flash access time settings. Power Library in SDK sets the flash wait states based on the frequency selected. [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C) Table 16. Static characteristics: Power consumption in active mode [6] Tamb = 40 C to +105 C, unless otherwise specified. VBAT_PMU = VBAT_DCDC = VDD = 3.0 V Symbol Parameter Conditions Min Typ[1] Max Unit ARM Cortex-M33 (CPU0) in active mode; ARM Cortex-M33 (CPU1) in sleep mode IDD supply current CoreMark code executed from SRAMX; flash powered down CCLK = 12 MHz [2][3] -0.9 -mA CCLK = 48 MHz [2][3] -2.1 -mA CCLK = 60 MHz [2][3] -2.3 -mA CCLK = 96 MHz [2][3] -3.4 -mA CCLK = 100 MHz [3][4] -3.5 -mA CCLK = 150 MHz [3][4] -6.2 -mA IDD supply current CoreMark code executed from flash; CCLK = 12 MHz; 2 system clock flash access time. [2][3][7] -0.95 - mA CCLK = 48 MHz, 5 system clock flash access time. [2][3][7] -2.4 -mA CCLK = 60 MHz, 6 system clock flash access time. [2][3][7] -2.6 -mA CCLK = 96 MHz, 8 system clock flash access time. [2][3][7] -3.4 -mA CCLK = 100 MHz, 8 system clock flash access time. [3][4][7] -3.5 -mA CCLK = 150 MHz, 12 system clock flash access time. [3][4][7] -5.9 -mA Table 17. Static characteristics: Power consumption in sleep mode Tamb = 40 C to +105 C, unless otherwise specified. VBAT_PMU = VBAT_DCDC = VDD = 3.0 V Symbol Parameter Conditions Min Typ[1] Max Unit ARM Cortex-M33 (CPU0) in sleep mode; ARM Cortex-M33 (CPU1) OFF (in reset, clock disabled) IDD supply current CCLK = 12 MHz, PLL disabled [1][2] -0.7 -mA CCLK = 96 MHz, PLL disabled [2] -2.7 -mA |
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