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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC55S6X датащи(PDF) 62 Page - NXP Semiconductors |
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LPC55S6X датащи(HTML) 62 Page - NXP Semiconductors |
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62 / 128 page  LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.9 — 10 February 2020 62 of 128 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller • Eight 32-bit general purpose registers can retain data in deep power-down. These registers are reset only on software reset of the RTC. 7.28.5 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 7.28.5.1 Features • 24-bit interrupt timer. • Four channels independently counting down from individually set values. • Repeat interrupt, one-shot interrupt, and one-shot bus stall modes. 7.28.6 OS Timer 42-bit free running timer with individual match/capture and interrupt generation logic used as continuous time-base for the system, available in any reduced power modes. It runs on 32kHz clock source, allowing a count period of more than 4 years. 7.28.6.1 Features • Central 42-bit, free-running gray-code event/timestamp timer. • Match registers compared to the main counter to generate an interrupt and/or wake-up event. • Capture registers triggered by CPU command, readable via the AHB/IPS bus. • APB interface for register access. • IRQ and wake-up. • Reads of gray-encoded timers are accomplished with no synchronization latency. 7.28.7 Micro-tick timer (UTICK) The ultra-low power Micro-tick Timer, running from the Watchdog oscillator, can be used to wake up the device from sleep and deep-sleep modes. 7.28.7.1 Features • Ultra simple timer. • Write once to start. • Interrupt or software polling. • Four capture registers that can be triggered by external pin transitions. 7.29 Digital peripherals 7.29.1 DMA controller The DMA controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional DMA transfers for a single source and destination. |
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