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LPC55S6X датащи(PDF) 98 Page - NXP Semiconductors

номер детали LPC55S6X
подробное описание детали  32-bit Arm Cortex짰-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,Flexcomm Interface, SDIO, 32-bit counter/ timers,SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
PDF  128 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S6X датащи(HTML) 98 Page - NXP Semiconductors

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LPC55S6x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 1.9 — 10 February 2020
98 of 128
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
12.2 16-bit ADC characteristics
[1]
Linear data collected using a linear histogram technique.
[2]
The values listed are typical values and are not guaranteed. Based on characterization. Not tested in
production.
[3]
fclk(ADC) = 24 MHz, STS = 3, Power select = 1, Average setting = 1, fs = 1 Msample/s
[4]
Differential linear results assume offset 0.2% from VREFL and 0.2% from VREFH
[5]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
[6]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors.
[7]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve.
[8]
The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve.
Table 37.
16-bit ADC static characteristics
Tamb = 40 C to +105 C; VDDA = 1.8 V to 3.6 V; ADC calibrated at T = 25C.
Symbol
Parameter
Conditions
Min[2]
Typ[2]
Max[2]
Unit
VIA
analog input
voltage
0-
VDDA
V
Cia
analog input
capacitance
12-bit mode
-
4
-
pF
16-bit mode
-
8
-
pF
fclk(ADC)
ADC clock
frequency
-24
MHz
fs
sampling
frequency
-
-
1.0
Msamples/s
ED
differential
linearity error
16-bit differential mode,
CTYPE = 2
[1][2][3][4][5] -0.99
-
2.6
LSB
16-bit single ended mode,
CTYPE = 1
[1][2][3][4][5] -1
+9.5
LSB
EL(adj)
integral
non-linearity
16-bit differential mode,
CTYPE = 2
[1][2][3][4][6] -16
-
+16
LSB
16-bit single ended mode,
CTYPE = 1
[1][2][3][4][6] -12
-
+12
LSB
EO
offset error
uncalibrated
[1][7] -2.3
-
mV
Verr(FS)
full-scale error
voltage
uncalibrated
[1][8] -24
-
LSB
ENOB
[L:] Effective
number of bits
16-bit differential mode,
CTYPE = 2
[9] -
12.6
-
bits
16-bit single ended mode,
CTYPE = 1
[9] -
12.0
-
bits
THD
[L:] Total
Harmonic
Distortion
16-bit differential mode,
CTYPE = 2
[9] --85
-
dB
16-bit single endedmode,
CTYPE = 1
[9] --85
-
dB
SFDR
[L:] Spurious Free
Dynamic Range
16-bit differential mode,
CTYPE = 2
[9] -86
-
dB
16-bit single ended mode,
CTYPE = 1
[9] -82
-
dB



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