LPC55S6X datasheet(73/128 Pages) NXP

номер детали	LPC55S6X

подробное описание детали	32-bit Arm Cortex짰-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,Flexcomm Interface, SDIO, 32-bit counter/ timers,SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG

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производитель	NXP [NXP Semiconductors]

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LPC55S6x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.9 — 10 February 2020

73 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

10.2 CoreMark data

[1]

Clock source FRO. PLL disabled

[2]

Characterized through bench measurements using typical samples.

[3]

Compiler settings: Keil v.5.28, optimization level 3, optimized for time on.

[4]

See the FLASHCFG register in the LPC55S6x User Manual for system clock flash access time settings. Power Library in SDK sets the

flash wait states based on the frequency selected.

[5]

PLL enabled

[6]

For device revision 1B, power library in SDK sets the DCDC output based on the frequency selected. For frequencies 100 MHz or

below, DCDC output is set between 1.0 V to 1.075 V, for frequencies between 101 MHz to 130 MHz, DCDC output is set between 1.025

V to 1.150 V and for frequencies above 130 MHz, DCDC output is set between 1.050 V to 1.2 V. For device revision 0A, the default

typical DCDC output is 1.1 V and for device revision 1B, the typical default DCDC output is 1.0 V.

Table 15.

CoreMark score [6]

Tamb =25C, VBAT_PMU = VBAT_DCDC = VDD = 3.0 V

Parameter

Conditions

Typ [2]

Unit

ARM Cortex-M33 (CPU0) in active mode; ARM Cortex-M33 (CPU1) in sleep mode

CoreMark score

CoreMark code executed from SRAMX;

CCLK = 12 MHz

[1][3]

4.0

(Iterations/s) / MHz

CCLK = 48 MHz

[1][3]

4.0

(Iterations/s) / MHz

CCLK = 60 MHz

[1][3]

4.0

(Iterations/s) / MHz

CCLK = 96 MHz

[1][3]

4.0

(Iterations/s) / MHz

CCLK = 100 MHz

[3][5]

4.0

(Iterations/s) / MHz

CCLK = 150 MHz

[3][5]

4.0

(Iterations/s) / MHz

CoreMark score

CoreMark code executed from flash;

CCLK = 12 MHz; 2 system clock flash

access time.

[1][3][4]

3.6

(Iterations/s) / MHz

CCLK = 48 MHz, 5 system clock flash

access time.

[1][3][4]

3.0

(Iterations/s) / MHz

CCLK = 60 MHz, 6 system clock flash

access time.

[1][3][4]

2.5

(Iterations/s) / MHz

CCLK = 96 MHz, 8 system clock flash

access time.

[1][3][4]

2.3

(Iterations/s) / MHz

CCLK = 100 MHz, 8 system clock flash

access time.

[3][4][5]

2.3

(Iterations/s) / MHz

CCLK = 150 MHz, 12 system clock flash

access time.

[3][4][5]

2.0

(Iterations/s) / MHz

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