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LPC55S6X датащи(PDF) 82 Page - NXP Semiconductors

номер детали LPC55S6X
подробное описание детали  32-bit Arm Cortex짰-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,Flexcomm Interface, SDIO, 32-bit counter/ timers,SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
PDF  128 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S6X датащи(HTML) 82 Page - NXP Semiconductors

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LPC55S6x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 1.9 — 10 February 2020
82 of 128
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
11. Dynamic characteristics
11.1 Flash memory
[1]
Number of erase/program cycles.
[2]
Flash operations (erase, blank check, program) and reading single word can only be performed for CPU
frequencies of up to 100 MHz. Cannot be performed for frequencies above 100 MHz.
11.2 I/O pins
[1]
Based on characterized, not tested in production
[2]
Rise and fall times measured between 90% and 10% of the full input signal level.
[3]
The slew rate is configured in the IOCON block the SLEW bit. See the LPC55S6x user manual.
Table 23.
Flash characteristics[2]
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Nendu
endurance
Page erase/program,
Tamb = 40 C to +85 C
[1] 100000 -
-
cycles
Mass erase/program,
Tamb = 40 C to +85 C
100000 -
-
cycles
Page erase/program
Tamb = 40 C to +105 C,
10000
-
-
cycles
Mass erase/program
Tamb = 40 C to +105 C,
10000
-
-
cycles
tret
retention time < 1k erase/program cycles
25
-
-
years
≥ 1k erase/program cycles
15
-
-
years
ter
erase time
1 page or multiple pages
-
2.0
-
ms
tprog
programming
time
-1.09
-
ms
Table 24.
Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +105 C; 1.8 V VDD 3.6 V
Symbol Parameter Conditions
Min
Typ Max
Unit
Standard I/O pins - normal drive strength
tr
rise time
pin configured as output; SLEW = 1
[2][3] 2.0
-
4.0
ns
tf
fall time
pin configured as output; SLEW = 1
[2][3] 2.0
-4.0
ns
tr
rise time
pin configured as output; SLEW = 0
[2][3] 1.2
-11.0
ns
tf
fall time
pin configured as output; SLEW = 0
[2][3] 3.9
-9.0
ns
I2C I/O pins - normal drive strength
tr
rise time
pin configured as output; SLEW = 1
[2][3] 3.0
-
11.0
ns
tf
fall time
pin configured as output; SLEW = 1
[2][3] 3.0
-7.0
ns
tr
rise time
pin configured as output; SLEW = 0
[2][3] 21.5
-39.0
ns
tf
fall time
pin configured as output; SLEW = 0
[2][3] 29.8
-36.0
ns



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