LPC55S6X datasheet(63/128 Pages) NXP

63 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

63 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

Two identical DMA controllers are provided on the LPC55S6x. The user may elect to

dedicate one of these to CPU0 and the other for use by the CPU1 and/or one may be

used as a secure DMA the other non-secure.

7.29.1.1 Features

• DMA0: 22 channels, 21 of which are connected to peripheral DMA requests. These

come from the Flexcomm (USART, SPI, I2C, and I2S), high-speed SPI interface,

ADC, AES, and SHA interfaces. 22 trigger sources are available.

• DMA1: 10 channels, 9 of which are connected to peripheral DMA requests. These

come from the Flexcomm Interfaces (0, 1, and 3), high-speed SPI interface, AES, and

SHA interfaces. 15 trigger sources are available.

• DMA operations can be triggered by on-chip or off-chip events.

• Priority is user selectable for each channel (up to eight priority levels).

• Continuous priority arbitration.

• Address cache with four entries.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

7.29.2 Programmable Logic Unit (PLU)

The PLU is comprised of 26 5-input LUT elements. Each LUT element contains a 32-bit

truth table (look-up table) register and a 32:1 multiplexer. During operation, the five LUT

inputs control the select lines of the multiplexer. This structure allows any desired logical

combination of the five LUT inputs.

7.29.2.1 Features

• The Programmable Logic Unit is used to create small combinatorial and/or sequential

logic networks including simple state machines.

• The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table

(LUT) elements, and four flip-flops.

• Eight primary outputs can be selected using a multiplexer from among all of the LUT

outputs and the four flip-flops.

• An external clock to drive the four flip-flops must be applied to the PLU_CLKIN pin if a

sequential network is implemented.

• Programmable logic can be used to drive on-chip inputs/triggers through external

pin-to-pin connections.

• A tool suite is provided to facilitate programming of the PLU to implement the logic

network described in a Verilog RTL design.

• Any of the eight selected PLU outputs can be enabled to contribute to an

asynchronous wake-up or an interrupt request from sleep and deep-sleep modes.

7.29.3 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings

supports several CRC standards commonly used. To save system power and bus

bandwidth, the CRC engine supports DMA transfers.

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