LPC55S6X datasheet(85/128 Pages) NXP

номер детали	LPC55S6X

подробное описание детали	32-bit Arm Cortex짰-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,Flexcomm Interface, SDIO, 32-bit counter/ timers,SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG

PDF	128 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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85 / 128 page

LPC55S6x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.9 — 10 February 2020

85 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

[4]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5]

Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[6]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[7]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[8]

The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Fig 12. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

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