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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC55S6X датащи(PDF) 86 Page - NXP Semiconductors |
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LPC55S6X датащи(HTML) 86 Page - NXP Semiconductors |
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86 / 128 page  LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.9 — 10 February 2020 86 of 128 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller 11.9 I2S-bus interface [1] Based on simulation; not tested in production. [2] Clock Divider register (DIV) = 0x0. [3] Typical ratings are not guaranteed. [4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section in the I2S chapter (UM11126) to calculate clock and sample rates. [5] Based on simulation. Not tested in production. Table 31. Dynamic characteristics: I2S-bus interface pins [1][4] Tamb = 40 C to 105 C; VBAT_DCDC = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50% level of the rising or falling edge. Symbol Parameter Conditions Min Typ[3] Max Unit Common to master and slave tWH pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5] (Tcyc/2) -1 - (Tcyc/2) +1 ns tWL pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5] (Tcyc/2) -1 - (Tcyc/2) +1 ns Master; 1.8 V VDD 3.6 V tv(Q) data output valid time on pin I2Sx_TX_SDA [2] 5 - 15 ns on pin I2Sx_WS 5 - 12 ns tsu(D) data input set-up time on pin I2Sx_RX_SDA [2] 4- - ns th(D) data input hold time on pin I2Sx_RX_SDA [2] 0- - ns Slave; 1.8 V VDD 3.6 V tv(Q) data output valid time on pin I2Sx_TX_SDA [2] 9 - 26 ns tsu(D) data input set-up time on pin I2Sx_RX_SDA [2] 4- - ns on pin I2Sx_WS 4- - ns th(D) data input hold time on pin I2Sx_RX_SDA [2] 0- - ns on pin I2Sx_WS 0- - ns |
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