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LPC55S6X датащи(PDF) 54 Page - NXP Semiconductors |
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LPC55S6X датащи(HTML) 54 Page - NXP Semiconductors |
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54 / 128 page ![]() LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.9 — 10 February 2020 54 of 128 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller Features • USB2.0 full-speed device controller supporting crystal-less operation in device mode using software library example in technical note (TN00063). • Supports ten physical (five logical) endpoints including one control endpoint. • Single and double-buffering supported. • Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. • Supports wake-up from Deep-sleep mode on USB activity and remote wake-up. • Supports SoftConnect. • Link Power Management (LPM) supported. 7.26.1.2 USB0 host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. Features • OHCI compliant. • Two downstream ports. 7.26.2 High-Speed USB Host/Device Interface (USB1) The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. 7.26.2.1 USB1 device controller The device controller enables 480 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. Features • Fully compliant with USB 2.0 Specification (high speed). • Supports 8 physical (16 logical) endpoints with up to 8 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • While USB is in the Suspend mode, the LPC55S6x can enter deep-sleep mode and wake up on USB activity. • Double buffer implementation for Bulk and Isochronous endpoints |
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