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LPC55S6X датащи(PDF) 88 Page - NXP Semiconductors

номер детали LPC55S6X
подробное описание детали  32-bit Arm Cortex짰-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,Flexcomm Interface, SDIO, 32-bit counter/ timers,SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
PDF  128 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S6X датащи(HTML) 88 Page - NXP Semiconductors

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LPC55S6x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 1.9 — 10 February 2020
88 of 128
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
11.10 SPI interface (Flexcomm Interfaces 0 - 7)
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading.
Excluding delays introduced by external device and PCB, the maximum supported bit rate
for SPI master mode (transmit/receive) is 50 Mbit/s.
Excluding delays introduced by external device and PCB, the maximum supported bit rate
for SPI slave receive mode is 25 Mbit/s and for slave transmit mode is 50 Mbits/s.
[1]
Based on simulated values. Not tested in production
Table 32.
SPI dynamic characteristics[1]
Tamb = 40 C to 105 C; VDD = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
fast mode for all pins;. Parameters sampled at the 50% level of the rising or falling edge.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master
tDS
data set-up time
5
-
-
ns
tDH
data hold time
0
-
-
ns
tv(Q)
data output valid time
5
-
13
ns
SPI slave
tDS
data set-up time
5
-
-
ns
tDH
data hold time
0
-
-
ns
tv(Q)
data output valid time
8
-
21
ns



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