LPC55S6X datasheet(48/128 Pages) NXP

48 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

48 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.22.3 Clock generation

The system control block facilitates the clock generation. Many clocking variations are

possible. Figure 5 gives an overview of potential clock options. Table 10 describes signals

on the clocking diagram. The maximum clock frequency is 150 MHz.

Remark: The indicated clock multiplexers shown in Figure 5 are synchronized. In order to

operate, the currently selected clock must be running, and the clock to be switched to

must also be running. This is so that the multiplexer can gracefully switch between the two

clocks without glitches. Other clock multiplexers are not synchronized. The output divider

can be stopped and restarted gracefully during switching if a glitch-free output is needed.

The low-power oscillator provides a frequency in the range of 1 MHz. The accuracy of this

clock is limited to +/- 15% over temperature, voltage, and silicon processing variations

after trimming made during assembly. To determine the actual watchdog oscillator output,

use the frequency measure block.

The part contains one system PLL that can be configured to use a number of clock inputs

and produce an output clock in the range of 1.2 MHz up to the maximum chip frequency,

and can be used to run most on-chip functions. The output of the PLL can be monitored

through the CLKOUT pin.

Table 10.

Clocking diagram signal name descriptions

Name

Description

32k_osc The 32 kHz output of the RTC oscillator. The 32 kHz clock must be enabled in the RTCOSCCTRL register.

clk_in

This is the internal clock that comes from the external oscillator.

frg_clk

The output of each Fractional Rate Generator to Flexcomm clock. Each FRG and its source selection is shown in

Figure 5.

fro_12m 12 MHz divided down from the currently selected on-chip FRO oscillator.

fro_hf

The currently selected FRO high speed output at 96 MHz.

main_clk The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source

selection are shown in Figure 5.

mclk_in

The MCLK input function, when it is connected to a pin by selecting it in the IOCON block.

pll0_clk

The output of the PLL0. The PLL0 and its source selection is shown in Figure 5.

pll1_clk

The output of the PLL1. The PLL1 and its source selection is shown in Figure 5.

fro_1m

The output of the low power oscillator.

“none”

A tied-off source that should be selected to save power when the output of the related multiplexer is not used.

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