LPC55S6X datasheet(52/128 Pages) NXP

52 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

52 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

All SRAM, logic state, and registers maintain their internal states. All SRAM instances that

are not configured to enter in ‘retention state’ will stay in active state.

7.23.4 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power

domain, the RESET pin, 4 Wake-up pins, and the OT Timer if enabled. Clock sources

such as FRO 32 KHz, and the 32.768 kHz RTC clock can be enabled or disabled via

software. The LPC55S6x can wake up from deep power-down mode via the RESET pin,

the RTC alarm, four special wake-up pins, or without an external signal, by using the

time-out of the OS Timer. The ALARM1HZ flag in RTC control register generates an RTC

wake-up interrupt request, which can wake up the part. SRAM can maintain their internal

states. All SRAM instances that are not configured to enter in ‘retention state’ will stay in

active state. In deep power-down mode all functional pins are in tri-state.

7.24 General Purpose I/O (GPIO)

The LPC55S6x provide GPIO ports 0 and 1 with a total of 64 GPIO pins.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The current level

of a port pin can be read back no matter what peripheral is selected for that pin.

See Table 3 “Pin description” for the default state on reset.

7.24.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set, clear, and toggle registers allow a single instruction set, clear or toggle of

any number of bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt

request.

• Two GPIO group interrupts can be triggered by a combination of any pin or pins to

reflect two distinct interrupt patterns.

• The grouped interrupts can wake up the part from sleep, deep-sleep, and power-down

modes.

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