LPC55S6X datasheet(53/128 Pages) NXP

53 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

53 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.25 Pin interrupt/pattern engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC. The pattern match engine can be used in

conjunction with software to create complex state machines based on pin inputs. Any

digital pin, independent of the function selected through the switch matrix can be

configured through the SYSCON block as an input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the I/O+ bus for fast single-cycle access.

7.25.1 Features

• Pin interrupts:

– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as

edge-sensitive or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH-active or LOW-active.

– Pin interrupts can wake up the device from sleep mode, and deep-sleep mode.

• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

– Each bit slice minterm (product term) comprising of the specified boolean

expression can generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

7.26 Communication peripherals

7.26.1 Full-speed USB Host/Device Interface (USB0)

The USB is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

7.26.1.1 USB0 device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory. The serial

interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

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