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LPC55S6X датащи(PDF) 64 Page - NXP Semiconductors

номер детали LPC55S6X
подробное описание детали  32-bit Arm Cortex짰-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,Flexcomm Interface, SDIO, 32-bit counter/ timers,SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
PDF  128 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S6X датащи(HTML) 64 Page - NXP Semiconductors

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LPC55S6x
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© NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 1.9 — 10 February 2020
64 of 128
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
7.29.3.1 Features
Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
Programmable seed number setting.
Supports CPU PIO or DMA back-to-back transfer.
Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation.
– 16-bit write: 2-cycle operation (8-bit x 2-cycle).
– 32-bit write: 4-cycle operation (8-bit x 4-cycle).
7.30 Analog peripherals
7.30.1 16-bit Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 16-bit and fast conversion rates of up to 1.0
Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple
sources.
7.30.1.1 Features
16-bit Linear successive approximation algorithm.
Differential operation with 16-bit or 13-bit resolution.
Single-ended operation with 16-bit or 12-bit resolution.
Support for two simultaneous single ended conversions.
Channel support for up to 64 analog input channels for conversion of external pin and
from internal sources.
Select external pin inputs paired for conversion as differential channel input.
Measurement of on-chip analog sources such as DAC, temperature sensor or
bandgap.
Configurable analog input sample time.
Configurable speed options to accommodate operation in low power modes of SoC.
Trigger detect with up to 16 trigger sources with priority level configuration. Software
or hardware trigger option for each.
Fifteen command buffers allow independent options selection and channel sequence
scanning.
Automatic compare for less-than, greater-than, within range, or out-of-range with
"store on true" and "repeat until true" options.
Two independent result FIFOs each contains 16 entries. Each FIFO has configurable
watermark and overflow detection.
Interrupt, DMA, or polled operation.



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