LPC55S6X datasheet(61/128 Pages) NXP

61 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

61 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.28.3 Windowed WatchDog Timer (WWDT)

The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a

programmable time if it enters an erroneous state. When enabled, a watchdog reset is

generated if the user program fails to feed (reload) the Watchdog within a predetermined

amount of time.

7.28.3.1 Features

• Internally resets chip if not reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Programmable 24-bit timer with internal fixed pre-scaler.

• Selectable time period from 1,024 watchdog clocks (TWDCLK × 256 × 4) to over 67

million watchdog clocks (TWDCLK × 224 × 4) in increments of four watchdog clocks.

• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog

reset to be disabled.

• Incorrect feed sequence causes immediate watchdog event if enabled.

• The watchdog reload value can optionally be protected such that it can only be

changed after the “warning interrupt” time is reached.

• Flag to indicate Watchdog reset.

• The watchdog clock (WDCLK) is generated from always on FRO_1MHz clock which

can be divided by WDT clock divider register. The accuracy of this clock is limited to

+/- 15% over temperature, voltage, and silicon processing variations.

• The Watchdog timer can be configured to run in Deep-sleep mode.

• Debug mode.

7.28.4 RTC timer

The RTC block to count seconds and generate an alarm interrupt to the processor

whenever the counter value equals the value programmed into the associated 32-bit

match register.

7.28.4.1 Features

• The RTC oscillator has the following clock outputs: 32.768 kHz clock (named as 32

kHz clock in rest of this chapter) 32 kHz clock, selectable for system clock and

CLKOUT pin, 1 Hz clock for RTC timing, and 1024 Hz clock (named as 1 kHz clock in

rest of this chapter) for high-resolution RTC timing.

• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.

• 15-bit, 32KHz sub-second counter.

• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution

with a more that one minute maximum time-out period.

• RTC alarm and high-resolution/wake-up timer time-out each generate independent

interrupt requests that go to one NVIC channel. Either time-out can wake up the part

from any of the low power modes, including deep power-down.

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