MT9072AB datasheet(37/275 Pages) ZARLINK

37 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

205

TDO

OH Test Data Output. Depending on the sequence previously applied to

the TMS input, the contents of either the instruction register or data

TDO is clocked on the falling edge of the TCK pulses. When no data is

shifted through the boundary scan cells, the TDO driver is set to a high

impedance state. See the pin description for TDI and the section on

JTAG.

206

TMS

IPu Test Mode Select Input. The logic signals received at the TMS input

are interpreted by the TAP Controller to control the test operations.

The TMS signals are sampled at the rising edge of the TCK pulse.

Internally pulled up to VDD. See the pin description for TDI and the

section on JTAG.

207

TCK

IPu Test Clock Input. TCK provides the clock for the test logic. The TCK

does not interfere with any on-chip clocks and thus remains

independent. The TCK permits shifting of test data into or out of the

Boundary-Scan register cells concurrently with the operation of the

device and without interfering with the on-chip logic. Internally pulled

up to VDD. See the pin description for TDI and the section on JTAG.

See Figure 30.

208

TRST

IPu Test Reset. When zero, the JTAG scan structure is reset. When one,

the JTAG scan structure operates normally. Internally pulled up to

VDD. See the pin description for TDI and the section on JTAG. A valid

device reset condition requires this input to be held low for a minimum

of 100 ns. This input is should be set to zero during initial power up,

then set to one if the JTAG port is to be used, otherwise, it may be

permanently set to zero.

RSV

This pin should be tied low.

Notes:

All inputs are CMOS with CMOS compatible logic levels.

All unused inputs should be tied low.

All outputs are CMOS and are compatible with CMOS logic levels.

See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for input and output voltage thresholds.

The number enclosed in parentheses following the pin name identifies the framer as follows:

[0] - framer 0, [1] - framer 1, [2] - framer 2,... [7] - framer 7

The “Y” character in the register address symbolizes the upper 4 address bits (A11A10A9A8) which identify the particular framer addressed

within the MT9072 as follows:

[0] 0000 - framer 0, [1] 0001 - framer 1,... [2] 0010 - framer 2,... [7] 0111 - framer 7

[8] 1000 - all 8 framers.

Pin types are as follows:

- input (5 V tolerant input

- input with a pullup or pulldown, these are 3 V tolerant inputs.

- output

I/O

- input and output

- output and high impedance

- output open drain

Pin Description (continued)

Pin #

Name

Type

Description (see Notes 1 to 7)

LQFP

LBGA

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