MT9072AB datasheet(66/275 Pages) ZARLINK

66 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

Y-bit is zero; when CAS multiframing is not acquired, the transmit Y-bit is one. Refer to ITU-T G.704 and G.732 for

more details on CAS multiframing requirements. Registers related to configuration and observation of the CAS

signaling are shown in Table 23.

Timeslot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to 15) is reserved for the

ABCD signaling bits for the 30 payload channels. The most significant nibbles are reserved for channels 1 to 15 and

the least significant nibbles are reserved for channels 16 to 30. That is, timeslot 16 of basic frame 1 has ABCD for

channel 1 and 16, timeslot 16 of basic frame 2 has ABCD for channel 2 and 17, through to timeslot 16 of basic

frame 15 has ABCD for channel 15 and 30. See Table 24. Note that the ABCD bits for TS1 to TS15 should not be

0000 to prevent mimic of the multiframe alignment signal(0000).

Address

Description

900

Global Control 0

CK1 determines an 8.192 Mbits stream or a 2.048 Mbits stream.

STBUS selects a GCI or ST-BUS CSTi, CSTo streams.

Y00

Alarm and Framing Control

Ensure that TAIS16 is off, the signaling information in CAS cannot be

sent if TAIS16 is on. Also signaling is not supported in IMA mode.

Y02

Interrupt and IO Control

If CSTo is to contain the signaling nibbles set CSTOE to 1 and RXCO to

Y03

DL,CCS,CAS and other

Control Register

RXTRS which sets the receiver in a transparent mode has to be turned

off.

Y04

Signaling Interrupt Period

Bit 0 and 1 of this register determine the period of the interrupt CASRI.

The period is selectable from 2 msec 8 msec and 16 msec.

Y05

CAS Control and Data

If RFL is set the receive signaling is frozen due to synchronization loss.

If debounce is selected a 14 msec debounce is applied before the

signaling is available in the csto or receive CAS register.

Y06

HDLC and CCS ST-BUS

Control Register

TS31E, TS15E and TS16E have to be off since Common Channel

signaling and CAS are mutually exclusive.

Y10

Synchronization and CRC-4

Remote Status.

MSYNC has to be low for the signaling in the Receive CAS Registers

or CSTO has valid data.

Y26

CAS, National, CRC-4 Local

and Timer Latch Status

The bit CASRL reflects the signaling changes on the receive CAS.

Y36

CAS, national, CRC-4 Local

and Timer Interrupt Status

The CASRI will be set if a signaling Interrupt has occurred. The period

of the interrupt is controlled by the signaling Interrupt Period

Y46

National Interrupt Mask

The bit CASRM can be used to mask interrupts from the receive

signaling changes.

Y51-Y6F Per Channel Transmit

Signaling

The clear channel bit can be used to block insertion of signaling in the

transmit direction. The CASS bit can be used to determine the source

of the transmit signaling, which is either the CSTi or the transmit

signaling ram.

Y90 to

YAF

Per Channel Timeslot

Control Register

The CASS bit determines the source of the transmit signaling which is

either the ST-BUS or the transmit signaling registers(Y51 to Y60).

Table 23 - Registers Related to CAS Signaling (E1)

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