MT9072AB datasheet(88/275 Pages) ZARLINK

88 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

13.2

E1 Error Counters

The MT9072 has eight error counters, which can be used for maintenance testing, and ongoing measurement of

the quality of a PCM30 link and to assist the designer in meeting specifications such as ITU-T I.431 and G.821. All

counters can be preset or cleared by writing to the appropriate locations. In addition, four error count latches are

provided which latch the counter data coincident with the one second status bit. Counters can automatically be

cleared (ACCLR register address Y03) after their data is latched. Associated with each counter is a maskable event

indication interrupt and a maskable counter overflow interrupt. Overflow interrupts are useful when cumulative error

counts are being recorded. For example, every time the frame error counter overflow (FEO) interrupt occurs, 256

frame errors have been received since the last FEO interrupt. The interrupt status register bits are cleared when

read. All non-latched error counters are cleared and by programming the counter clear bit (CNCLR register address

Y03) low to high. See Table 43 for counter events and relationship between the counters.

Address

Description

Y03

DL,CCS,CAS and other

Control Register

The CNCLR bit can be used to clear the non-latched counters.

the ACCLR can be used to automatically clear 1 sec counter.

Y15

PRBS Error Counter and

CRC-4 Multiframe Counter

PRBS counts bit errors and the CRC counter interval for each

received multiframe.

Y16

Loss of basic frame counter

Counter that is incremented once per 125 usec whenever bsync

is 1.

Y17

E-bit error counter

This counter counts the ebit errors.

Y18

Bipolar violation counter. This

counter counts the bipolar

violation outside the HDB3

coding.

This counter counts the bipolar violation outside the HDB3

coded zeros.

Y19

CRC-4 error counter

This counter is incremented for calculated crc-4 errors (CRCS1

and CRCS2).

Y1A

FAS bit error counter and FAS

error counter

This counter counts the FAS bit error and FAS errors.

Y28

E bit error counter latch

This counter is the one second latched version of Y17.

Y29

BPV error counter latch

This counter is a one second latched version of Y18.

Y2A

CRC-4 error counter latch

This counter is a one second latched version of Y19.

Y2B

FAS error counter latch

This counter is a one second latched version of Y1A.

Y36

CAS,National, CRC-4 local

and timer interrupt status

Oneseci is the one second interrupt status. This interrupt can be

used for performance monitoring.

Y46

CAS,National, CRC-4 local

and timer interrupt mask

Onesecm is the one second interrupt status. This interrupt can

be used for performance monitoring.

Table 42 - Registers Required for Observing and Clearing Error Counters (E1)

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