MT9072AB datasheet(57/275 Pages) ZARLINK

57 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

6.1

Transmit Elastic Buffer

In T1 mode, the MT9072 contains a transmit elastic buffer in addition to the receive elastic buffer. Data is clocked

into the transmit elastic buffer by the 2.048 Mbit/s or 8.192 Mbit/s ST-BUS clock (which is subsequently divided to a

2.048 MHz clock). The data is clocked out of the transmit elastic buffer by the 1.544 MHz clock input to the TXCL

pin.

The delay through the transmit elastic buffer will vary in accordance with the position of the channel in the frame.

For example, PCM24 channel 1 sits in the elastic buffer for approximately 1 usec, and PCM24 channel 24 sits in the

elastic buffer for approximately 32 usec. The relative phase delay between the system ST-BUS frame boundary

and the transmit elastic frame read boundary is measured every frame and reported in the Transmit Slip Buffer

Status Word (Y14). In addition, the relative delay between these frame boundaries may be programmed by writing

to Tx Set Delay Bits (register address YF7). Every write to the TX Set Delay Bits resets the Transmit Slip Buffer

MSB bit TxSBMSB (register address Y14). After a write, the delay through the slip buffer is less than 1 frame in

duration. Each write operation will result in a disturbance of the transmit PCM24 frame boundary, causing the far

end to go out of sync.

The transmit elastic buffer is capable of performing controlled slips in a manner similar to the receive elastic buffer.

Slips on the transmit side are independent of slips on the receive side. The two status bits. TSLIP and TSLPD

(register address Y14), give indication of a slip occurrence and direction. TSLP changes state in the event of a slip.

If TSLPD=0, the slip buffer has overflowed and a frame was lost; if TSLPD=1, an underflow condition occurred and

a frame was repeated. A maskable interrupt status bit TXSLIPI (register address Y36) is also provided. Under

normal operation no slips should occur in the transmit path. Slips will only occur if the input CKi clock has excess

wander relative to the input TXCL clock, or if the TX Set Delay Bits (register address YF7) register is initialized too

close to the slip pointers after system initialization.

7.0

Data Link

7.1

T1 Data Link

The ESF protocol allows for carrier messages to be embedded in the S-bit position. The MT9072 provides 3

separate means of controlling the Data Link.

• Transmit and receive Data Link pins TxDL, TxDLC, RxDL and RxDLC.

• Bit - Oriented Messages may be transmit and received via dedicated transmit and receive

registers(Y07,Y08,Y12). This is only applicable in the ESF mode.

• The ESF Data Link (DL) can be connected to an internal HDLC, operating at a bit rate of 4 kbits/sec. The

HDLC can be activated by setting the control bit 1(HDLCEn) of the HDLC & Data Link Control Word (Y06).

In the D4 mode the Fs bits can be inserted/extracted from the Data Link pins by setting the EDLEN bit in Y06. The

registers related to the Data Link are shown in Table 16.

MT9072AB датащи(PDF) 57 Page - Zarlink Semiconductor Inc