MT9072AB datasheet(72/275 Pages) ZARLINK

72 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

9.0

HDLC

The MT9072 has 1 embedded HDLC controller for each of the framers. Each controller may be attached to any

timeslot. The HDLC can also be connected to the FDL bits (T1 ESF Mode) for provision of a 4 Kbit/s Data Link or

Sa bits in E1 mode for data link up to 20 Kb/s.

The features of the HDLC are:

• Independent transmit and receive FIFO;

• Receive FIFO maskable interrupts for nearly full and overflow conditions;

• Transmit FIFO maskable interrupts for nearly empty and underflow conditions;

• Maskable interrupts for transmit end-of-packet and receive end-of-packet;

• Maskable interrupts for receive bad-frame (includes frame abort);

• Transmit end-of-packet and frame-abort functions.

The relevant registers associated with HDLC are listed in Table 32.

Address

Description

Y06

HDLC and DataLink Control

The bits of this register determine whether the HDLC is connected

to the Data Link or payload.

YF2

HDLC Control

General configuration for the HDLC.

YF3

HDLC Test Control

Control bits for testing the HDLC such as loopbacks.

YF4

Address Recognition

Address recognition register for storing data in the Receive FIFO of

a packet that matches the received address.

YF5

Transmit FIFO

This register is used for writing data to the HDLC Transmit FIFO.

The data from the FIFO can be subsequently sent to Data Link or a

selected channel.

YF6

Transmit Byte Counter

This counter determines the size of the HDLC packet to be sent

when the cycle bit is set (YF2).

Y1D

HDLC Status

This register provides status on the FIFO’s.

Y1E

Receive CRC

This register provides the received FCS of a packet.

Y1F

Receive FIFO

This register has to be read to obtain the receive FIFO data.

Y23

HDLC Latch Status

These register bits are the latched version of the HDLC status.

Y33

HDLC Interrupt Status

This register provides the interrupt status of events such as

underflow, go ahead packet etc.

Y43

HDLC Interrupt Mask

These register bits can be used to mask HDLC events to cause

interrupts.

Table 32 - HDLC Related Registers

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