MT9072AB datasheet(52/275 Pages) ZARLINK

52 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

5.2.3

E1 Channel Associated Signaling (CAS) Multiframing (Timeslot 16)

Refer to the section on Channel Associated Signaling (CAS) Operation.

5.2.4

E1 Framing Algorithm

The MT9072 contains three distinct framing algorithms: basic frame alignment, signaling multiframe alignment and

CRC-4 multiframe alignment. Figure 7 is a state diagram that illustrates these algorithms and how they interact.

After power-up, the basic frame alignment framer will search for a frame alignment signal (FAS) in the PCM30

receive bit stream. Once the FAS is detected, the corresponding bit 2 of the non-frame alignment signal (NFAS) is

checked. If bit 2 of the NFAS is zero a new search for basic frame alignment is initiated. If bit 2 of the NFAS is one

and the next FAS is correct, the algorithm declares that basic frame synchronization has been found (status register

address Y10

bit BSYNC is reset to zero).

Once basic frame alignment is acquired the signaling and CRC-4 multiframe searches will be initiated. The

signaling multiframe algorithm will align to the first multiframe alignment signal pattern (MFAS = 0000) it receives in

the most significant nibble of channel 16 (status register address Y10 bit MSYNC is zero). Signaling multiframe

alignment will be lost when two consecutive multiframes are received in error.

The CRC-4 multiframe alignment signal is a 001011 bit sequence that appears in PCM30 bit position one of the

NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table 12). In order to achieved CRC-4 synchronization two consecutive

CRC-4 multiframe alignment signals must be received without error (status register address Y10 bit CSYNC is

zero).

The MT9072 framing algorithm supports automatic interworking of interfaces with and without CRC-4 processing

capabilities. That is, if an interface with CRC-4 capability, achieves valid basic frame alignment, but does not

AUTC

ARAI

TALM

Description

Automatic CRC-interworking is activated. If no valid CRC MFAS is being

received, transmit RAI will flicker high with every reframe (8 msec), this cycle

will continue for 400 msec., then transmit RAI will be low continuously. The

device will stop searching for CRC MFAS, continue to transmit CRC-4

remainders, stop CRC-4 processing, indicate CRC-to-non-CRC operation and

transmit E-bits to be the same state as the TE control bit (control register

address Y00).

010

Automatic CRC-interworking is activated. Transmit RAI is low continuously.

011

Automatic CRC-interworking is activated. Transmit RAI is high

continuously.

Automatic RAI is activated. Automatic CRC-interworking is de-activated. If

no valid CRC MFAS is being received, transmit RAI flickers high with every

reframe (8 msec), this cycle continues for 400 msec, then transmit RAI

becomes high continuously. The device continues to search for CRC MFAS

and transmit E-bits are the same state as the TE control bit. When CSYN = 0,

the CRC MFAS search is terminated and the transmit RAI goes low.

110

Automatic RAI is activated. Automatic CRC-interworking is de-activated.

Transmit RAI is low continuously.

111

Automatic RAI is activated. Automatic CRC-interworking is de-activated.

Transmit RAI is high continuously.

Table 13 - Operation of AUTC, ARAI and TALM Control Bits (E1)

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