MT9072AB datasheet(75/275 Pages) ZARLINK

75 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

9.1.8

HDLC Transmitter

Following initialization and enabling, the transmitter is in the Idle Channel state (Mark Idle), continuously sending

ones. Interframe Time Fill state (Flag Idle) is selected by setting the MI bit in register YF2 high1. The Transmitter

remains in either of these two states until data is written to the Tx FIFO. YF2 bits EOP (end of packet) and FA

(Frame Abort) are set as status bits before the microprocessor loads 8 bits of data into the 10 bit wide FIFO (8 bits

data and 2 bits status). To change the tag bits being loaded in the FIFO, HDLC Master Control must be written to

before writing to the FIFO. However, EOP and FA are reset after writing to the TX FIFO. The Transmit Byte Count

packet and decrements after every write to the Tx FIFO. When a count of one is reached, the next byte written to

the FIFO is tagged as an end of packet. The register may be made to cycle through the same count if the packets

are of the same length by setting HDLC Master Control bit Cycle.

If the transmitter is in the Idle Channel state when data is written to the Tx FIFO, then an opening flag is sent and

data from Tx FIFO follows. Otherwise, data bytes are transmitted as soon as the current flag byte has been sent. Tx

FIFO data bytes are continuously transmitted until either the FIFO is empty or an EOP or FA status bit is read by the

transmitter. After the last bit of the EOP byte has been transmitted, a 16-bit FCS is sent followed by a closing flag.

When multiple packets of data are loaded into Tx FIFO, only one flag is sent between packets. When the HDLC is

connected to FDL or a transmit channel

The least significant bit of the Transmit FIFO data is sent first on the serial stream.

Frame aborts (the transmission of 7F hex), are transmitted by tagging a byte previously written to the Tx FIFO.

When a byte has an FA tag, then an FA is sent instead of that tagged byte. That is, all bytes previous to but not

including that byte are sent. After a Frame Abort, the transmitter returns to the Mark Idle or Interframe Time Fill

state, depending on the state of the Mark idle control bit.

Tx FIFO underrun will occur if the FIFO empties and the last byte did not have either an EOP or FA tag. A frame

abort sequence will be sent when an underrun occurs.

Below is an example of the transmission of a three byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill). TXcen can

be enabled before or after this sequence.

(a) Write’0020’hex to Control Register 1

-Mark idle bit set

(b) Write’AA’ hex to TX FIFO

-Data byte

(d) Write’01A0’ hex to Control Register 1

-TXEN; EOP; Mark idle bits set

(e) Write’77’hex to TX FIFO

-Final data byte

The transmitter may be enabled independently of the receiver. This is done by setting the TXEN bit of the Control

completion of the transmission of the present packet; the contents of the FIFO are not cleared. Disabling will consist

of stopping the transmitter clock. The Status and Interrupt Registers may still be read and the FIFO and Control

Registers may be written to while the transmitter is disabled. The transmitted FCS may be inhibited using the Tcrci

bit of HDLC Master Control Register. In this mode the opening flag followed by the data and closing flag is sent and

zero insertion still included, but no CRC. That is, the FCS is injected by the microprocessor as part of the data field.

This is used in V.120 terminal adaptation for synchronous protocol sensitive UI frames.

1. If the MT9072A HDLC transmitter is set up in the Mark-Idle state (YF2 MI is 1) then it will occasionally (less than 1% of the

time) fail to transmit the opening flag when it is changed from the disabled state to the enabled state (YF2 TXEN changed

from 0 to1). A missing opening flag will cause the packet to be lost at the receiving end.

This problem only affects the first packet transmitted after the HDLC transmitter is enabled. Subsequent packets are

unaffected.

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