MT9072AB datasheet(27/275 Pages) ZARLINK

27 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

111

135

151

N15

H13

D15

TxDL[0]

TxDL[1]

TxDL[2]

TxDL[3]

TxDL[4]

TxDL[5]

TxDL[6]

TxDL[7]

Transmit Data Link. This pin accepts data from an external device for

the Transmit Data Link. Pins TxDL[0-7] are used for Framers[0-7]

respectively.

In T1 mode this pin accepts a 4 kbit/s serial input stream that contains

the ESF FDL (Facility Data Link) bits that are to be embedded in the

transmit data stream. The data is clocked in by the rising edge of the

clock provided at the TxDLC pin. TxDL data does not pass through the

transmit slip buffer.

In E1 mode this pin accepts a 4,8,12,16 or 20 kbit/s, as programmed

by the Datalink Control Register (Address Y08), data stream which

contains the data link national bits (timeslot 0, bits 4-8 of the NFAS

(Non-Frame Alignment Signal) frames) for transmission. The selected

data link national bits are clocked into the framer by the falling edge of

the clock provided at the TxDLC pin.

112

131

152

T10

N16

H14

D16

TxDLC[0]

TxDLC[1]

TxDLC[2]

TxDLC[3]

TxDLC[4]

TxDLC[5]

TxDLC[6]

TxDLC[7]

Transmit Data Link Clock. This pin provides a clock that is used to

clock transmit data link data out of an external device into the TxDL

pin. The TxDLC pin can also be configured as an enable signal. Pins

TxDLC[0-7] are used for Framers[0-7] respectively.

In T1 mode, this pin provides either a 4 kHz clock derived by gating

the 1.544 MHz clock provided to the TxCL pin, or it provides an enable

signal. The TxDLC pin can be configured as a clock or an enable

signal with the DLCK bit (Address Y06). Transmit data link data does

not pass through the transmit slip buffer. See Figure 47.

In E1 mode, this pin provides either a gapped 4,8,12,16 or 20 kHz

clock, as programmed by the Datalink Control Register (Address Y08),

derived by gating the 2.048 MHz clock provided to the TxCL pin, or it

provides an enable signal. The TxDLC pin can be configured as a

clock or an enable signal with the DLCK bit (Address Y08). See Figure

66.

Pin Description (continued)

Pin #

Name

Type

Description (see Notes 1 to 7)

LQFP

LBGA

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