MT9072AB datasheet(33/275 Pages) ZARLINK

33 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

118

138

158

N10

L14

G16

B14

CKi[1]

CKi[2]

CKi[3]

CKi[5]

CKi[6]

CKi[7]

System Clock. In 2.048 Mbit/s ST-BUS mode this pin accepts the

clock that is used to time the transmit side and receive side of the

framer. In IMA mode it accepts the clock that is used to time the

transmit side of the framer only. Pins CKi[0-7] are used to time

Framers[0-7] respectively. The CKi clock rate is determined by control

bits at (Address 900). This pin has no function in 8.192 Mbit/s mode.

In 2.048 Mbit/s ST-BUS mode this pin accepts the ST-BUS type

4.096 MHz clock that is used to time the data appearing at pins DSTi,

CSTi, DSTo and CSTo. See Figure 34.

In T1 IMA mode this pin accepts the 1.544 MHz clock that is used to

time the transmit data appearing at pin DSTi. IMA mode is selected by

setting the IMA bit (Address Y00) to 1. See Figure 40.

In E1 IMA mode this pin accepts the ST-BUS type 4.096 MHz clock

that is used to time the transmit data appearing at pins DSTi. IMA

mode is selected by setting the IMA bit (Address Y00) to 1. In T1/E1

IMA mode the receive data stream is clocked out of pin DSTo by the

clock output by pin RxDLC.

R13

FPi[0]

FPi[4]

Frame Pulse. This pin accepts a frame pulse that sets the basic frame

boundary for the transmit and receive sides of the framer. The clock

rate is determined by control bits at (Address 900)

In 2.048 Mbit/s mode and in IMA mode, operation is the same as that

described for pins FPi[1-3].

In 8.192 Mbit/s mode this pin accepts an 8.192 Mbit/s ST-BUS type

frame pulse which sets the frame boundary common to four framers.

FPi[0] is used to set the frame boundary for Framers[0-3] and FPi[4] is

used to set the frame boundary for Framers[4-7]. See Figure 36.

8.192 Mbit/s operation is not available in IMA mode.

Pin Description (continued)

Pin #

Name

Type

Description (see Notes 1 to 7)

LQFP

LBGA

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