MT9072AB datasheet(79/275 Pages) ZARLINK

79 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

10.1.4

Signaling Multiframe Boundary (RxMF, TxMF Pins)

Dedicated multiframe boundary pins are included which provide the user the option of setting the multiframe

boundaries and identifying the multiframe boundaries with an external device. Refer to the RxMF and TxMF pin

descriptions.

10.1.5

Control Pins

10.1.5.1

Reset Operation (RESET Pin, RST Bit and RSTC Bit)

The MT9072 can be reset using the hardware RESET pin or the software reset bits: RST (register address YF1)

and RSTC (address 900). The RST bit resets a particular framer and the RSTC bit is a global software reset bit.

On initial power up, a hard reset must be done using the RESET pin. A valid reset condition requires both of these

inputs to be held low for a minimum of 100 ns. These inputs should be set to zero during initial power up, then set to

one.

After initial power up, the MT9072 can be reset using the hardware RESET pin or the software reset bit RSTC

(register address 900). When the device emerges from its reset state, it will begin to function in T1 mode and the

control registers will be initialized as described in Table 36. Clearing the T1E0 bit in register 900 to place the

MT9072 in E1 mode will cause another internal reset and the control registers will be initialized to their E1 defaults

as described in Table 37. In addition, individual framers may be reset with the software reset bit RST. Using the

RST will reset the individual framer to its default E1 or T1 setting. RST will not affect the common control register

(9xx). All reset operations take 1 full frame (125 us) to complete. Refer to the RESET pin description, RSTC and

RST bit descriptions for additional details.

Address

Description

Y00

Framing Mode Select

Setting the IMA bit will cause the framer to enter IMA mode.

Y06

HDLC & Datalink Control

E1.5CK bit must be set to provide a 1.544 MHz clock on

RXDLC.

Table 35 - Registers Related to IMA Mode

Function

Status

Control Bits Reset Value

Address

Framing Mode

Mode D4,Reframe criteria is set for 2

bits errors in 4 bits,Fs bit is not

included in the synchronization

criteria, S-bit not included in CRC

calculation. The elastic stores are not

bypassed.

RELBY,TELBY,TRANSP,T1DM,ESF,SLC

96,CXC,RS10,FSI,ReFR,MFReFR,JTS,T

XSYNC =0

Y00

Line Coding and

Interface

The T1 interfaces are set to NRZ,

Bipolar,and Rising edge of clocks for

output and falling for input line

clocks.TxB8ZS and RxB8ZS and

Transmit PDV enforcer is turned off.

RZCS1:0,TZCS2:0TPDV,TXB8ZS,RXB8

ZS,ADSEQ,RZNRZ,UNIBI,CLKE = 0

Y01

Transmit Alarms All sending alarms are deactivated.

TESFYEL,TXSECY,TD4YEL,TAIS,

#,T1DMY,D4SECY,SO = 14

Y02

Table 36 - Reset Status (T1)

MT9072AB датащи(PDF) 79 Page - Zarlink Semiconductor Inc

MT9072AB датащи(HTML) 79 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL