MT9072AB datasheet(44/275 Pages) ZARLINK

44 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

Figure 6 - PCM30 Format (E1)

4.2

E1 Interface to the Physical Layer Device

interface formats are provided including RZ dual rail, NRZ dual rail and NRZ single rail.

RZ Dual Rail - On the Transmit side the pulse width is approximately half the duration of the PCM30 bit cell

centered around the falling edge of TXCL. On the receive side RPOS and RNEG are sampled on the falling edge of

EXCLi. Note that the T2OP bit in Register Y02 (selectable for edge sampling) has no effect in RZ mode.

NRZ Dual Rail - With this format, pulses are present for the full bit cell, which allows the set-up and hold times to be

easily met. For the receiver the sampling point can be the rising edge or the falling edge of the EXCLi clock

dependent on the CLKE bit in Register Y01. The transmitted data can be output either on the rising or falling edge

of TXCL selected by the T2OP bit. TXCL is an input in T1 mode and output in E1 mode.

NRZ Single Rail - This NRZ format is not dual rail, and therefore, only requires a single output line and a single

input line (i.e., TPOS and RPOS). The T2OP bit controls the TXCL clock edge and CLKE bit controls the

RPOS/RNEG sampling.

HDB3 - Register Control bit THDB3 (address Y02) determines the PCM30 encoding in the transmit direction. The

encoding can either be HDB3 or alternate mark inversion (AMI). The RHDB3 (address Y02) bit selects the receive

HDB3 decoding.

PCM30 Timeslot

1 2 3...15

17 18 19...31

PCM30 Voice/Data

Channels

1 2 3...15

16 17 18...30

Table 6 - PCM30 Timeslot to PCM30 Channel Relationship (E1)

FRAME

TIMESLOT

Most

Significant

Bit (First)

Least

Significant

Bit (Last)

BIT

FRAME

TIMESLOT

BIT

2.0 ms

(8/2.048)

µs

125

µs

•• •• •• ••

•• ••

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